NUC130LE3CN Nuvoton Technology Corporation of America, NUC130LE3CN Datasheet - Page 469

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NUC130LE3CN

Manufacturer Part Number
NUC130LE3CN
Description
IC MCU 32BIT 128KB FLASH 48LQFP
Manufacturer
Nuvoton Technology Corporation of America
Series
NuMicro™ NUC100r
Datasheets

Specifications of NUC130LE3CN

Core Processor
ARM Cortex-M0
Core Size
32-Bit
Speed
50MHz
Connectivity
CAN, I²C, IrDA, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
Number Of I /o
35
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Eeprom Size
-
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 5.5 V
Data Converters
A/D 8x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
48-LQFP
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

Available stocks

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Part Number
Manufacturer
Quantity
Price
Part Number:
NUC130LE3CN
Manufacturer:
Nuvoton Technology Corporation of America
Quantity:
10 000
Part Number:
NUC130LE3CN
Manufacturer:
NUVOTON
Quantity:
20 000
5.16.4.3 Single Mode
In single mode, A/D conversion is performed only once on the specified single channel. The
operations are as follows:
Note: If software enables more than one channel in single mode, the channel with the lowest number will be
selected and the other enabled channels will be ignored.
1.
2.
3.
4.
ADDRx[11:0]
NuMicro™ NUC130/NUC140 Technical Reference Manual
A/D conversion will be started when the ADST bit of ADCR is set to 1 by software or
external trigger input.
When A/D conversion is finished, the result is stored in the A/D data register
corresponding to the channel.
The ADF bit of ADSR register will be set to 1. If the ADIE bit of ADCR register is set to 1,
the ADC interrupt will be asserted.
The ADST bit remains 1 during A/D conversion. When A/D conversion ends, the ADST
bit is automatically cleared to 0 and the A/D converter enters idle state. Note that, after
clearing the ADST bit, the ADST bit must be kept at 0 at least one ADC clock period
before setting it to 1 again. If not, the A/D converter may not work.
ADC_CLK
sample
ADST
ADF
Figure 5-102 Single Mode Conversion Timing Diagram
1
Figure 5-101 ADC Clock Control
2
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8
9
Publication Release Date: June 14, 2011
20
ADDRx[11:0]
Revision V2.01

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