NUC130LE3CN Nuvoton Technology Corporation of America, NUC130LE3CN Datasheet - Page 94

• Manufacturer Part Number: NUC130LE3CN
• Description: IC MCU 32BIT 128KB FLASH 48LQFP
• Manufacturer: Nuvoton Technology Corporation of America
• Series: NuMicro™ NUC100r

Specifications of NUC130LE3CN

• Core Processor: ARM Cortex-M0
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: CAN, I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 35
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 8x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-LQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

5.2.7.1
Table 5-2 lists the exception model supported by NuMicro™ NUC100 Series. Software can set
four levels of priority on some of these exceptions as well as on all interrupts. The highest user-
configurable priority is denoted as “0” and the lowest priority is denoted as “3”. The default priority
of all the user-configurable interrupts is “0”. Note that priority “0” is treated as the fourth priority on
the system, after three system exceptions “Reset”, “NMI” and “Hard Fault”.
Number
Vector
0 ~ 15
16
17
18
19
20
21
22
23
24
25
Exception Model and System Interrupt Map
NuMicro™ NUC130/NUC140 Technical Reference Manual
Interrupt (IRQ0 ~ IRQ31)
(Bit in Interrupt
Exception Name
Registers)
Interrupt
Number
Hard Fault
Reserved
Reserved
PendSV
SysTick
SVCall
Reset
0
1
2
3
4
5
6
7
8
9
-
NMI
GPCDE_INT
PWMA_INT
PWMB_INT
GPAB_INT
BOD_OUT
TMR0_INT
TMR1_INT
WDT_INT
Interrupt
EINT0
EINT1
Name
-
Table 5-2 Exception Model
Brown-Out Brown-Out low voltage detected interrupt
Source IP Interrupt description
PWM0~3 PWM0, PWM1, PWM2 and PWM3 interrupt
PWM4~7 PWM4, PWM5, PWM6 and PWM7 interrupt
TMR0
TMR1
GPIO
GPIO
GPIO
GPIO
- 94 -
WDT
-
Vector Number
12 ~ 13
16 ~ 47
System exceptions
Watchdog Timer interrupt
External signal interrupt from PB.14 pin
External signal interrupt from PB.15 pin
External signal interrupt from PA[15:0]/PB[13:0]
External interrupt from PC[15:0]/PD[15:0]/PE[15:0]
Timer 0 interrupt
Timer 1 interrupt
4 ~ 10
11
14
15
1
2
3
Publication Release Date: June 14, 2011
Configurable
Configurable
Configurable
Configurable
Reserved
Reserved
Priority
Revision V2.01
-3
-2
-1