NUC130LE3CN Nuvoton Technology Corporation of America, NUC130LE3CN Datasheet - Page 374

• Manufacturer Part Number: NUC130LE3CN
• Description: IC MCU 32BIT 128KB FLASH 48LQFP
• Manufacturer: Nuvoton Technology Corporation of America
• Series: NuMicro™ NUC100r

Specifications of NUC130LE3CN

• Core Processor: ARM Cortex-M0
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: CAN, I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 35
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 8x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-LQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

5.13.5.5 Software Control of CAN_TX Pin
5.13.6 CAN Communications
5.13.6.1 Managing Message Objects
this mode, the C_CAN runs without the Message RAM.
The IF1 Registers are used as Transmit Buffer. The transmission of the contents of the IF1
Registers are requested by writing the Busy bit of the IF1 Command Request Register to one.
The IF1 Registers are locked while the Busy bit is set. The Busy bit indicates that the
transmission is pending.
As soon the CAN bus is idle, the IF1 Registers are loaded into the shift register of the CAN Core
and the transmission is started. When the transmission has been completed, the Busy bit is reset
and the locked IF1 Registers are released.
A pending transmission can be aborted at any time by resetting the Busy bit in the IF1 Command
Request Register while the IF1 Registers are locked. If the software has reset the Busy bit, a
possible retransmission in case of lost arbitration or in case of an error is disabled.
The IF2 Registers are used as a Receive Buffer. After the reception of a message the contents of
the shift register is stored into the IF2 Registers, without any acceptance filtering.
Additionally, the actual contents of the shift register can be monitored during the message
transfer. Each time a read Message Object is initiated by writing the Busy bit of the IF2
Command Request Register to one, the contents of the shift register are stored into the IF2
Registers.
In Basic Mode, the evaluation of all Message Object related control and status bits and the control
bits of the IFn Command Mask Registers are turned off. The message number of the Command
request registers is not evaluated. The NewDat and MsgLst bits in the IF2 Message Control
Register retain their function, DLC3-0 indicates the received DLC, and the other control bits are
read as ‘0’.
Four output functions are available for the CAN transmit pin, CAN_TX . In addition to its default
function (serial data output), the CAN transmit pin can drive the CAN Sample Point signal to
monitor CAN_Core’s bit timing and it can drive constant dominant or recessive values. The latter
two functions, combined with the readable CAN receive pin CAN_RX , can be used to check the
physical layer of the CAN bus.
The output mode for the CAN_TX pin is selected by programming the Tx1 and Tx0 bits of the
CAN Test Register.
The three test functions of the CAN_TX pin interfere with all CAN protocol functions. CAN_TX
must be left in its default function when CAN message transfer or any of the test modes (Loop
Back Mode, Silent Mode, or Basic Mode) are selected.
The configuration of the Message Objects in the Message RAM (with the exception of the bits he
CAN Control Regist MsgVal , NewDat , IntPnd , and TxRqst ) will not be affected by resetting the
chip. All the Message Objects must be initialized by the application software or they must be “not
valid” ( MsgVal = ‘0’) and the bit timing must be configured before the application software clears
the Init bit in ter.
The configuration of a Message Object is done by programming Mask, Arbitration, Control and
Data fields of one of the two interface registers to the desired values. By writing to the
corresponding IFn Command Request Register, the IFn Message Buffer Registers are loaded
into the addressed Message Object in the Message RAM.
When the Init bit in the CAN Control Register is cleared, the CAN Protocol Controller state
NuMicro™ NUC130/NUC140 Technical Reference Manual
- 374 -
Publication Release Date: June 14, 2011
Revision V2.01