NUC130LE3CN Nuvoton Technology Corporation of America, NUC130LE3CN Datasheet - Page 394

• Manufacturer Part Number: NUC130LE3CN
• Description: IC MCU 32BIT 128KB FLASH 48LQFP
• Manufacturer: Nuvoton Technology Corporation of America
• Series: NuMicro™ NUC100r

Specifications of NUC130LE3CN

• Core Processor: ARM Cortex-M0
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: CAN, I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 35
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 8x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-LQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

5.13.7 Register Description
5.13.8 Register Map
The C_CAN allocates an address space of 256 bytes. The registers are organized as 16-bit
registers.
The two sets of interface registers (IF1 and IF2) control the software access to the Message RAM.
They buffer the data to be transferred to and from the RAM, avoiding conflicts between software
accesses and message reception/transmission.
R : read only, W : write only, R/W : both read and write
Register
CAN0_BA = 0x4018_0000
CAN_CON
CAN_STATUS
CAN_ERR
CAN_BTIME
CAN_IIDR
CAN_TEST
CAN_BRPE
CAN_IF1_CREQ
CAN_IF2_CREQ
CAN_IF1_CMASK
CAN_IF2_CMASK
CAN_IF1_MASK1
CAN_IF2_MASK1
CAN_IF1_MASK2
CAN_IF2_MASK2
CAN_IF1_ARB1
CAN_IF2_ARB1
CAN_IF1_ARB2
CAN_IF2_ARB2
CAN_IF1_MCON
CAN_IF2_MCON
CAN_IF1_DAT_An/
CAN_IF1_DAT_Bn/
CAN_IF2_DAT_An/
CAN_IF2_DAT_Bn/
NuMicro™ NUC130/NUC140 Technical Reference Manual
Offset
CAN0_BA+0x00
CAN0_BA+0x04
CAN0_BA+0x08
CAN0_BA+0x0C
CAN0_BA+0x10
CAN0_BA+0x14
CAN0_BA+0x18
CAN0_BA+0x20
CAN0_BA+0x80
CAN0_BA+0x24
CAN0_BA+0x84
CAN0_BA+0x28
CAN0_BA+0x88
CAN0_BA+0x2C
CAN0_BA+0x8C
CAN0_BA+0x30
CAN0_BA+0x90
CAN0_BA+0x34
CAN0_BA+0x94
CAN0_BA+0x38
CAN0_BA+0x98
CAN0_BA+0x3C~40
CAN0_BA+0x44~48
CAN0_BA+0x9C~A0
CAN0_BA+0xA4~A8
R/W
R/W
R/W
R
R/W
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
Control Register
Status Register
Error Counter
Bit Timing Register
Interrupt Identifier Register
Test Register
BRP Extension Register
IFn
IFn Command Mask Registers
IFn Mask 1 Register
IFn Mask 2 Register
IFn Arbitration 1 Register
IFn Arbitration 2 Register
IFn Message Control Registers
IFn Data An
eg: CAN_IF1_DAT_A1 = CAN_BA+0x3Ch
- 394 -
CAN_IF1_DAT_A2 = CAN_BA+0x40h
(*2)
Command Request Registers
(*3)
and Data Bn
Publication Release Date: June 14, 2011
(*3)
Registers
Revision V2.01
Reset Value
0x0000_0001
0x0000_0000
0x0000_0000
0x0000_2301
0x0000_0000
*
0x0000_0000
0x0000_0001
0x0000_0000
0x0000_FFFF
0x0000_FFFF
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
(1)