DSP-DEVKIT-2S60 Altera, DSP-DEVKIT-2S60 Datasheet - Page 31

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DSP-DEVKIT-2S60

Manufacturer Part Number
DSP-DEVKIT-2S60
Description
Manufacturer
Altera
Datasheet

Specifications of DSP-DEVKIT-2S60

Lead Free Status / Rohs Status
Not Compliant
Board Components & Interfaces
Altera Corporation
August 2006
Table 20
SDRAM Memory (U39 & U40)
The SDRAM devices (U39 and U40) are memory devices with PC100
functionality and self refresh mode. The SDRAM is fully synchronous
with all signals registered on the positive edge of the system clock.
The SDRAM device pins are connected to the Stratix II device. An
SDRAM controller peripheral is included with the Stratix II DSP
Development Kit, allowing a Nios II processor to view the SDRAM
devices as a large, linearly-addressable memory.
Table 21
Board reference
Device description
A0
A1
A2
A3
A4
A5
A6
A7
FLASH_CS_N
FLASH_OE_N
FLASH_RW_N
flash_WP_n
Table 20. Flash Memory Reference
Table 21. SDRAM Device (U39) Pin-Outs (Part 1 of 3)
Table 19. Flash Memory (U17) (Part 2 of 2)
Pin Name
Pin Name
lists the reference information for the Flash memory.
lists the Stratix II device pin-outs for SDRAM device U39.
Item
Reference Manual
Pin Number Connects to Stratix II Pin
25
26
27
60
61
62
63
64
U17
Flash Memory
Pin Number
Description
AA32
AA31
W32
Y30
AD11
AD13
AC14
AD14
AB13
AE14
AB14
AE10
Stratix II Development Board
2–21