DSP-DEVKIT-2S60 Altera, DSP-DEVKIT-2S60 Datasheet - Page 35

• Manufacturer Part Number: DSP-DEVKIT-2S60
• Manufacturer: Altera

Specifications of DSP-DEVKIT-2S60

• Lead Free Status / Rohs Status: Not Compliant

Board Components & Interfaces
Altera Corporation
August 2006
Table 23
Ethernet MAC/PHY (U16)
The LAN91C111 (U16) is a mixed signal analog/digital device that
implements protocols at 10 Mbps and 100 Mbps. The control pins of U16
are connected to the Stratix II device so that user logic (e.g., the Nios II
processor) can access Ethernet via the RJ-45 connector (RJ1). Refer to
Table 24
DQM3
RAS_N
CAS_N
CKE
CS_N
Board reference
Device description
ENET_ADS_N
ENET_AEN
ENET_BE_N0
ENET_BE_N1
ENET_BE_N2
ENET_BE_N3
ENET_DATACS_N
ENET_INTRQ0
ENET_IOCHRDY
ENET_IOR_N
ENET_IOW_N
Table 22. SDRAM Device (U40) Pin-Outs (Part 3 of 3)
Table 23. SDRAM Memory Reference
Table 24. Ethernet MAC/PHY (U16) (Part 1 of 3)
Pin Name
lists the reference information for the SDRAM memory.
for Stratix II pin-outs for Ethernet MAC/PHY device U16.t
Pin Name
Item
Reference Manual
Pin Number
59
19
18
67
20
Pin Number
Connects to Stratix II Pin
U39, U40
SDRAM Memory
AC25
AD25
AD24
AC24
AA25
AE26
AE25
AB23
AB26
T20
V26
Description
AC12
AK4
AL8
AL7
AL6
Stratix II Development Board
2–25