SC28L202A1DGG/G,11 NXP Semiconductors, SC28L202A1DGG/G,11 Datasheet - Page 18

• Manufacturer Part Number: SC28L202A1DGG/G,11
• Description: IC UART DUAL W/FIFO 56-TSSOP
• Manufacturer: NXP Semiconductors
• Series: IMPACTr

Specifications of SC28L202A1DGG/G,11

• Features: False-start Bit Detection
• Number Of Channels: 2, DUART
• Fifo's: 256 Byte
• Voltage - Supply: 3.3V, 5V
• With Parallel Port: Yes
• With Auto Flow Control: Yes
• With False Start Bit Detection: Yes
• With Modem Control: Yes
• With Cmos: Yes
• Mounting Type: Surface Mount
• Package / Case: 56-TFSOP (0.240", 6.10mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 935279792118; SC28L202A1DGG/G-T; SC28L202A1DGG/G-T

Philips Semiconductors
The several automatic controls. These modes are concerned with
the recognition of the address character itself
The enabling of the wake-up mode executes a partial enabling of the
receiver state machine. Even though the receiver has been reset the
wake up mode will over ride the disable and reset conditions.
Receiver Reset and Disable
Receiver disable stops the receiver immediately – data being
assembled in the receiver shift register is lost. Data and status in the
FIFO is preserved and may be read. A re-enable of the receiver
after a disable will cause the receiver to begin assembling
characters at the next start bit detected.
Receiver reset will discard the present shift register data, reset the
receiver ready bit (RxRDY), clear the status of the byte at the top of
the FIFO and re-align the FIFO read/write pointers. This effectively
‘clears’ the receiver FIFO although the FIFO data is not altered.
Receiver Watchdog Timer
A ‘watchdog timer’ is associated with each receiver. Its interrupt is
enabled by the ‘watchdog’ bits of the ‘Watch Dog, Character
Address, and X enable’ register (WCXER). The purpose of this timer
is to alert the control processor that characters are in the RxFIFO
which have not been read and/or the data stream has stopped. This
situation may occur at the end of a transmission when the last few
characters received are not sufficient to cause an interrupt. This
counter times out after 64 bit times. It is reset each time a read of
the RxFIFO is executed.
Receiver Time-out Mode
In addition to the watch dog timer described in the receiver section,
the counter/timer may be used for a similar function. Its
programmability, of course, allows much greater precision of timeout
intervals.
The time-out mode uses the received data stream to control the
counter. Each time a received character is transferred from the shift
register to the RxFIFO, the counter is restarted. If a new character is
not received before the counter reaches zero count, the counter
ready bit is set, and an interrupt can be generated. This mode can
be used to indicate when data has been left in the RxFIFO for more
than the programmed time limit. Otherwise, if the receiver has been
programmed to interrupt the CPU when the receive FIFO is full, and
the message ends before the FIFO is full, the CPU may not know
there is data left in the FIFO. The CTPU and CTPL value would be
programmed for just over one character time, so that the CPU would
be interrupted as soon as it has stopped receiving continuous data.
2005 Nov 01
MR3 [1:0] = 01 Auto wake. Enable receiver on address
recognition for this station. Upon recognition of its assigned
address the local receiver will be enabled by the character
recognition state machine and normal receiver communications
with the host will be established.
MR3 [1:0] = 10 Auto Doze. Disable receiver on address
recognition, not for this station. Upon recognition of an address
character that is not its own, in the Auto Doze mode, the receiver
will be disabled by the character recognition state machine and
the address just received either discarded or loaded to the
RxFIFO depending on the programming of MR0 [6].
MR3 [1:0] = 11 Auto wake and doze. Both modes described
above. The programming of MR3 [1:0] to 11 will enable both the
auto wake and auto doze features.
Dual UART
12
This mode can also be used to indicate when the serial line has
been marking for longer than the programmed time limit. In this
case, the CPU has read all of the characters from the FIFO, but the
last character received has started the count. If there is no new data
during the programmed time interval, the counter ready bit will get
set, and an interrupt can be generated.
Writing the appropriate command to the command register enables
the time-out mode. Writing an ‘Ax’ to CR A or CR B will invoke the
time-out mode for that channel. Writing a 0xCx to CR A or CR B will
disable the time-out mode. CTPU and CTPL should be loaded with a
count-down value that, with the selected clock, will generate a time
period greater than the normal receive character period. The
time-out mode disables the regular START/STOP Counter
commands and puts the C/T into counter mode under the control of
the received data stream. Each time a received character is
transferred from the shift register to the RxFIFO, the C/T is stopped
after 1 C/T clock, reloaded with the value in CTPU and CTPL and
then restarted on the next C/T clock. If the C/T is allowed to end the
count before a new character has been received, the counter ready
bit, ISR [3], will be set. If IMR [3] is set, interrupt arbitration for the
C/T will begin. Invoking the ‘Set Time-out Mode On’ command, CRx
= ‘Ax’, clears the counter ready bit and stop the counter until the
next character is received.
Exiting the time mode will clear the counter ready bit.
Arbitrating Interrupt Structure
(NOTE: The advantages and intelligence of this system may be
completely defeated by merely setting the arbitration value in the
ICR to 0x00 and not using the CIR. One would then rely on
traditional interrupt service by searching and testing various status
registers on the assertion of the IRQN.)
The interrupt system determines when an interrupt should be
asserted thorough an arbitration (or bidding) system. This arbitration
is exercised over the several systems within the DUART that may
generate an interrupt. These will be referred to as ‘interrupt sources’.
There are 18 in all and may of those have several sub-levels. In
general the arbitration is based on the fill level of the receiver FIFO
or the empty level of the transmitter FIFO. The FIFO levels are
encoded into an 8-bit number, which is concatenated to the channel
number and source identification code. All of this is compared (via
the bidding or arbitration process) to a user defined ‘threshold’.
Whenever a source exceeds the numerical value of the threshold
the interrupt will be generated.
Interrupt sources that do not have a FIFO are each provided with a
‘programmable field’ that will determine their importance in the
arbitration and type identification process. (See Table 1 below)
At the time of interrupt acknowledge (IACKN) the source which has
the highest bid (not necessarily the source that caused the interrupt
to be generated) will be captured in a ‘Current Interrupt Register’
(CIR). This register will contain the complete definition of the
interrupting source: channel, types of interrupt (receiver, transmitter,
change of state, etc.) and FIFO fill level. The value of the bits in the
CIR are used to drive the interrupt vector and global registers such
that controlling processor may be steered directly to the proper
service routine. A single read operation to the CIR provides all the
information needed to qualify and quantify the most common
interrupt sources.
SC28L202
Product data sheet