AT32UC3A0128AU Atmel Corporation, AT32UC3A0128AU Datasheet - Page 100
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AT32UC3A0128AU
Manufacturer Part Number
AT32UC3A0128AU
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT32UC3A0128.pdf
(98 pages)
2.AT32UC3A0128.pdf
(826 pages)
3.AT32UC3A0128.pdf
(377 pages)
4.AT32UC3A0128.pdf
(33 pages)
5.AT32UC3A0128.pdf
(159 pages)
6.AT32UC3A0128AU.pdf
(2 pages)
Specifications of AT32UC3A0128AU
Flash (kbytes)
128 Kbytes
Pin Count
144
Max. Operating Frequency
66 MHz
Cpu
32-bit AVR
# Of Touch Channels
32
Hardware Qtouch Acquisition
No
Max I/o Pins
109
Ext Interrupts
109
Usb Transceiver
1
Usb Speed
Full Speed
Usb Interface
Device + OTG
Spi
6
Twi (i2c)
1
Uart
4
Ssc
1
Ethernet
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
384
Resistive Touch Screen
No
Dac Channels
2
Dac Resolution (bits)
16
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
32
Self Program Memory
YES
External Bus Interface
1
Dram Memory
sdram
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
3.0-3.6 or (1.65-1.95+3.0-3.6)
Operating Voltage (vcc)
3.0-3.6 or (1.65-1.95+3.0-3.6)
Fpu
No
Mpu / Mmu
Yes / No
Timers
10
Output Compare Channels
16
Input Capture Channels
6
Pwm Channels
13
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Available stocks
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Company:
Part Number:
AT32UC3A0128AU-U
Manufacturer:
ATMEL
Quantity:
4
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16.3.1
16.3.2
16.3.3
Non maskable interrupts
CPU response
Clearing an interrupt request
oritize between them. All of the input lines in each group are logically-ORed together to form the
GrpReqN lines, indicating if there is a pending interrupt in the corresponding group.
The Request Masking hardware maps each of the GrpReq lines to a priority level from INT0 to
INT3 by associating each group with the INTLEVEL field in the corresponding IPR register. The
GrpReq inputs are then masked by the I0M, I1M, I2M, I3M and GM mask bits from the CPU sta-
tus register. Any interrupt group that has a pending interrupt of a priority level that is not masked
by the CPU status register, gets its corresponding ValReq line asserted.
The Prioritizer hardware uses the ValReq lines and the INTLEVEL field in the IPRs to select the
pending interrupt of the highest priority. If a NMI interrupt is pending, it automatically gets high-
est priority of any pending interrupt. If several interrupt groups of the highest pending interrupt
level have pending interrupts, the interrupt group with the highest number is selected.
Interrupt level (INTLEVEL) and handler autovector offset (AUTOVECTOR) of the selected inter-
rupt are transmitted to the CPU for interrupt handling and context switching. The CPU doesn't
need to know which interrupt is requesting handling, but only the level and the offset of the han-
dler address. The IRR registers contain the interrupt request lines of the groups and can be read
via PB for checking which interrupts of the group are actually active.
Masking of the interrupt requests is done based on five interrupt mask bits of the CPU status
register, namely interrupt level 3 mask (I3M) to interrupt level 0 mask (I0M), and Global interrupt
mask (GM). An interrupt request is masked if either the Global interrupt mask or the correspond-
ing interrupt level mask bit is set.
A NMI request has priority over all other interrupt requests. NMI has a dedicated exception vec-
tor address defined by the AVR32 architecture, so AUTOVECTOR is undefined when
INTLEVEL indicates that an NMI is pending.
When the CPU receives an interrupt request it checks if any other exceptions are pending. If no
exceptions of higher priority are pending, interrupt handling is initiated. When initiating interrupt
handling, the corresponding interrupt mask bit is set automatically for this and lower levels in sta-
tus register. E.g, if interrupt on level 3 is approved for handling the interrupt mask bits I3M, I2M,
I1M, and I0M are set in status register. If interrupt on level 1 is approved the masking bits I1M,
and I0M are set in status register. The handler offset is calculated from AUTOVECTOR and
EVBA and a change-of-flow to this address is performed.
Setting of the interrupt mask bits prevents the interrupts from the same and lower levels to be
passed trough the interrupt controller. Setting of the same level mask bit prevents also multiple
request of the same interrupt to happen.
It is the responsibility of the handler software to clear the interrupt request that caused the inter-
rupt before returning from the interrupt handler. If the conditions that caused the interrupt are not
cleared, the interrupt request remains active.
Clearing of the interrupt request is done by writing to registers in the corresponding peripheral
module, which then clears the corresponding NMIREQ/IREQ signal.
The recommended way of clearing an interrupt request is a store operation to the controlling
peripheral register, followed by a dummy load operation from the same register. This causes a
AT32UC3A
100
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