AT32UC3A0128AU Atmel Corporation, AT32UC3A0128AU Datasheet - Page 524
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AT32UC3A0128AU
Manufacturer Part Number
AT32UC3A0128AU
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT32UC3A0128.pdf
(98 pages)
2.AT32UC3A0128.pdf
(826 pages)
3.AT32UC3A0128.pdf
(377 pages)
4.AT32UC3A0128.pdf
(33 pages)
5.AT32UC3A0128.pdf
(159 pages)
6.AT32UC3A0128AU.pdf
(2 pages)
Specifications of AT32UC3A0128AU
Flash (kbytes)
128 Kbytes
Pin Count
144
Max. Operating Frequency
66 MHz
Cpu
32-bit AVR
# Of Touch Channels
32
Hardware Qtouch Acquisition
No
Max I/o Pins
109
Ext Interrupts
109
Usb Transceiver
1
Usb Speed
Full Speed
Usb Interface
Device + OTG
Spi
6
Twi (i2c)
1
Uart
4
Ssc
1
Ethernet
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
384
Resistive Touch Screen
No
Dac Channels
2
Dac Resolution (bits)
16
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
32
Self Program Memory
YES
External Bus Interface
1
Dram Memory
sdram
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
3.0-3.6 or (1.65-1.95+3.0-3.6)
Operating Voltage (vcc)
3.0-3.6 or (1.65-1.95+3.0-3.6)
Fpu
No
Mpu / Mmu
Yes / No
Timers
10
Output Compare Channels
16
Input Capture Channels
6
Pwm Channels
13
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AT32UC3A0128AU-U
Manufacturer:
ATMEL
Quantity:
4
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32058K AVR32-01/12
Figure 30-24. Pipe Activation Algorithm
30.7.3.7
30.7.3.8
Address Setup
Remote Wake-Up
As long as the pipe is not correctly configured (CFGOK = 0), the controller can not send packets
to the device through this pipe.
The CFGOK bit is set by hardware only if the configured size and number of banks are correct
compared to their maximal allowed values for the pipe (see
maximal FIFO size (i.e. the DPRAM size).
See
Once the pipe is correctly configured (CFGOK = 1), only the PTOKEN and INTFRQ bit-fields can
be modified by software. INTFRQ is meaningless for non-interrupt pipes.
When starting an enumeration, the firmware gets the device descriptor by sending a
GET_DESCRIPTOR USB request. This descriptor contains the maximal packet size of the
device default control endpoint (bMaxPacketSize0) and the firmware re-configures the size of
the default control pipe with this size parameter.
Once the device has answered the first host requests with the default device address 0, the host
assigns a new address to the device. The host controller has to send a USB reset to the device
and to send a SET_ADDRESS(addr) SETUP request with the new address to be used by the
device. Once this SETUP transaction is over, the firmware writes the new address into the
HADDR bit-field. All following requests, on all pipes, will be performed using this new address.
When the host controller sends a USB reset, the HADDR bit-field is reset by hardware and the
following host requests will be performed using the default device address 0.
The controller host mode enters the Suspend state when the SOFE bit is cleared. No more
“Start of Frame” is sent on the USB bus and the USB device enters the Suspend state 3 ms
later.
The device awakes the host by sending an Upstream Resume (Remote Wake-Up feature).
When the host controller detects a non-idle state on the USB bus, it raises the Host Wake-Up
Section 30.7.1.6 on page 506
Pipe Activated
Yes
CFGOK ==
PENX = 1
Activation
UPCFGX
PEPNUM
PTOKEN
INTFRQ
PTYPE
ALLOC
PSIZE
Pipe
PBK
1?
No
ERROR
for more details about DPRAM management.
Enable the pipe.
Configure the pipe:
Allocate the configured DPRAM
banks.
Test if the pipe configuration is
correct.
- interrupt request frequency;
- endpoint number;
- type;
- token;
- size;
- number of banks.
Table 30-1 on page
AT32UC3A
497) and to the
524
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