AT32UC3A0128AU Atmel Corporation, AT32UC3A0128AU Datasheet - Page 118
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AT32UC3A0128AU
Manufacturer Part Number
AT32UC3A0128AU
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT32UC3A0128.pdf
(98 pages)
2.AT32UC3A0128.pdf
(826 pages)
3.AT32UC3A0128.pdf
(377 pages)
4.AT32UC3A0128.pdf
(33 pages)
5.AT32UC3A0128.pdf
(159 pages)
6.AT32UC3A0128AU.pdf
(2 pages)
Specifications of AT32UC3A0128AU
Flash (kbytes)
128 Kbytes
Pin Count
144
Max. Operating Frequency
66 MHz
Cpu
32-bit AVR
# Of Touch Channels
32
Hardware Qtouch Acquisition
No
Max I/o Pins
109
Ext Interrupts
109
Usb Transceiver
1
Usb Speed
Full Speed
Usb Interface
Device + OTG
Spi
6
Twi (i2c)
1
Uart
4
Ssc
1
Ethernet
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
384
Resistive Touch Screen
No
Dac Channels
2
Dac Resolution (bits)
16
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
32
Self Program Memory
YES
External Bus Interface
1
Dram Memory
sdram
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
3.0-3.6 or (1.65-1.95+3.0-3.6)
Operating Voltage (vcc)
3.0-3.6 or (1.65-1.95+3.0-3.6)
Fpu
No
Mpu / Mmu
Yes / No
Timers
10
Output Compare Channels
16
Input Capture Channels
6
Pwm Channels
13
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AT32UC3A0128AU-U
Manufacturer:
ATMEL
Quantity:
4
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18.4.7
18.5
Flash commands
Writing words to a page that is not completely erased
The page buffer is also used for writes to the User page.
Write operations can be prevented by programming the Memory Protection Unit of the CPU.
Writing 8-bit and 16-bit data to the page buffer is not allowed and may lead to unpredictable
data corruption.
Page buffer write operations are performed with 4 wait states.
Writing to the page buffer can only change page buffer bits from one to zero, ie writing
0xaaaaaaaa to a page buffer location that has the value 0x00000000, will not change the page
buffer value. The only way to change a bit from zero to one, is to reset the entire page buffer
with the Clear Page Buffer command.
The page buffer is not automatically reset after a page write. The programmer should do this
manually by issuing the Clear Page Buffer flash command. This can be done after a page
write, or before the page buffer is loaded with data to be stored to the flash page.
Example: Writing a word into word address 130 of a flash with 128 words in the page buffer.
PAGEN will be updated with the value 1, and the word will be written into word 2 in the page
buffer.
This can be used for EEPROM emulation, i.e. writes with granularity of one word instead of an
entire page. Only words that are in an completely erased state (0xFFFFFFFF) can be
changed. The procedure is as follows:
The FLASHC offers a command set to manage programming of the flash memory, locking and
unlocking of regions, and full flash erasing. See chapter 18.8.3 for a complete list of
commands.
To run a command, the field CMD of the Flash Command Register (FCMD) has to be written
with the command number. As soon as the FCMD register is written, the FRDY flag is auto-
matically cleared. Once the current command is complete, the FRDY flag is automatically set.
If an interrupt has been enabled by setting the bit FRDY in FCR, the interrupt line of the flash
controller is activated. All flash commands except for Quick Page Read (QPR) will generate an
interrupt request upon completion if FRDY is set.
After a command has been written to FCMD, the programming algorithm should wait until the
command has been executed before attempting to read instructions or data from the flash or
writing to the page buffer, as the flash will be busy. The waiting can be performed either by
polling the Flash Status Register (FSR) or by waiting for the flash ready interrupt. The com-
mand written to FCMD is initiated on the first clock cycle where the HSB bus interface in
FLASHC is IDLE. The user must make sure that the access pattern to the FLASHC HSB inter-
face contains an IDLE cycle so that the command is allowed to start. Make sure that no bus
masters such as DMA controllers are performing endless burst transfers from the flash. Also,
make sure that the CPU does not perform endless burst transfers from flash. This is done by
1. Clear page buffer
2. Write to the page buffer the result of the logical bitwise AND operation between the
3. Write Page.
contents of the flash page and the new data to write. Only words that were in an
erased state can be changed from the original page.
AT32UC3A
118
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