AT32UC3A0128AU Atmel Corporation, AT32UC3A0128AU Datasheet - Page 523
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AT32UC3A0128AU
Manufacturer Part Number
AT32UC3A0128AU
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT32UC3A0128.pdf
(98 pages)
2.AT32UC3A0128.pdf
(826 pages)
3.AT32UC3A0128.pdf
(377 pages)
4.AT32UC3A0128.pdf
(33 pages)
5.AT32UC3A0128.pdf
(159 pages)
6.AT32UC3A0128AU.pdf
(2 pages)
Specifications of AT32UC3A0128AU
Flash (kbytes)
128 Kbytes
Pin Count
144
Max. Operating Frequency
66 MHz
Cpu
32-bit AVR
# Of Touch Channels
32
Hardware Qtouch Acquisition
No
Max I/o Pins
109
Ext Interrupts
109
Usb Transceiver
1
Usb Speed
Full Speed
Usb Interface
Device + OTG
Spi
6
Twi (i2c)
1
Uart
4
Ssc
1
Ethernet
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
384
Resistive Touch Screen
No
Dac Channels
2
Dac Resolution (bits)
16
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
32
Self Program Memory
YES
External Bus Interface
1
Dram Memory
sdram
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
3.0-3.6 or (1.65-1.95+3.0-3.6)
Operating Voltage (vcc)
3.0-3.6 or (1.65-1.95+3.0-3.6)
Fpu
No
Mpu / Mmu
Yes / No
Timers
10
Output Compare Channels
16
Input Capture Channels
6
Pwm Channels
13
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AT32UC3A0128AU-U
Manufacturer:
ATMEL
Quantity:
4
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32058K AVR32-01/12
30.7.3.3
30.7.3.4
30.7.3.5
30.7.3.6
USB Reset
Device Detection
Pipe Reset
Pipe Activation
The controller enters the Suspend state when the USB bus is in a “Suspend” state, i.e. when the
host mode does not generate the “Start of Frame”. In this state, the USB consumption is mini-
mal. The host mode exits the Suspend state when starting to generate the SOF over the USB
line.
A device is detected by the USB controller host mode when D+ or D- is no longer tied low, i.e.
when the device D+ or D- pull-up resistor is connected. To enable this detection, the host con-
troller has to provide the VBus power supply to the device by setting the VBUSRQ bit (by setting
the VBUSRQS bit).
The device disconnection is detected by the host controller when both D+ and D- are pulled
down.
The USB controller sends a USB bus reset when the firmware sets the RESET bit. The USB
Reset Sent interrupt (RSTI) is raised when the USB reset has been sent. In this case, all the
pipes are disabled and de-allocated.
If the bus was previously in a “Suspend” state (SOFE = 0), the USB controller automatically
switches it to the “Resume” state, the Host Wake-Up interrupt (HWUPI) is raised and the SOFE
bit is set by hardware in order to generate SOFs immediately after the USB reset.
A pipe can be reset at any time by setting its PRSTX bit in the UPRST register. This is recom-
mended before using a pipe upon hardware reset or when a USB bus reset has been sent. This
resets:
The pipe configuration remains active and the pipe is still enabled.
The pipe reset may be associated with a clear of the data toggle sequence. This can be
achieved by setting the RSTDT bit (by setting the RSTDTS bit).
In the end, the firmware has to clear the PRSTX bit to complete the reset operation and to start
using the FIFO.
The pipe is maintained inactive and reset (see
long as it is disabled (PENX = 0). The Data Toggle Sequence bit-field (DTSEQ) is also reset.
The algorithm represented on
•the internal state machine of this pipe;
•the receive and transmit bank FIFO counters;
•all the registers of this pipe (UPCFGX, UPSTAX, UPCONX), except its configuration (ALLOC,
PBK, PSIZE, PTOKEN, PTYPE, PEPNUM, INTFRQ) and its Data Toggle Sequence bit-field
(DTSEQ).
Figure 30-24
must be followed in order to activate a pipe.
Section 30.7.3.5 on page 523
AT32UC3A
for more details) as
523
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