AT32UC3A0128AU Atmel Corporation, AT32UC3A0128AU Datasheet - Page 514
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AT32UC3A0128AU
Manufacturer Part Number
AT32UC3A0128AU
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT32UC3A0128.pdf
(98 pages)
2.AT32UC3A0128.pdf
(826 pages)
3.AT32UC3A0128.pdf
(377 pages)
4.AT32UC3A0128.pdf
(33 pages)
5.AT32UC3A0128.pdf
(159 pages)
6.AT32UC3A0128AU.pdf
(2 pages)
Specifications of AT32UC3A0128AU
Flash (kbytes)
128 Kbytes
Pin Count
144
Max. Operating Frequency
66 MHz
Cpu
32-bit AVR
# Of Touch Channels
32
Hardware Qtouch Acquisition
No
Max I/o Pins
109
Ext Interrupts
109
Usb Transceiver
1
Usb Speed
Full Speed
Usb Interface
Device + OTG
Spi
6
Twi (i2c)
1
Uart
4
Ssc
1
Ethernet
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
384
Resistive Touch Screen
No
Dac Channels
2
Dac Resolution (bits)
16
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
32
Self Program Memory
YES
External Bus Interface
1
Dram Memory
sdram
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
3.0-3.6 or (1.65-1.95+3.0-3.6)
Operating Voltage (vcc)
3.0-3.6 or (1.65-1.95+3.0-3.6)
Fpu
No
Mpu / Mmu
Yes / No
Timers
10
Output Compare Channels
16
Input Capture Channels
6
Pwm Channels
13
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Available stocks
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Quantity
Price
Company:
Part Number:
AT32UC3A0128AU-U
Manufacturer:
ATMEL
Quantity:
4
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32058K AVR32-01/12
30.7.2.10
30.7.2.10.1 Special Considerations for Control Endpoints
30.7.2.10.2 STALL Handshake and Retry Mechanism
30.7.2.11
30.7.2.11.1 Overview
STALL Request
Management of Control Endpoints
• The firmware may then set the RMWKUP bit to send an upstream resume to the host for a
• When the controller sends the upstream resume, the Upstream Resume interrupt (UPRSM) is
• RMWKUP is cleared by hardware at the end of the upstream resume.
• If the controller detects a valid “End of Resume” signal from the host, the End of Resume
For each endpoint, the STALL management is performed using:
To answer the next request with a STALL handshake, STALLRQ has to be set by setting the
STALLRQS bit. All following requests will be discarded (RXOUTI, etc. will not be set) and hand-
shaked with a STALL until the STALLRQ bit is cleared, what is done by hardware when a new
SETUP packet is received (for control endpoints) or when the STALLRQC bit is set.
Each time a STALL handshake is sent, the STALLEDI flag is set by the USB controller and the
EPXINT interrupt is raised.
If a SETUP packet is received into a control endpoint for which a STALL is requested, the
Received SETUP interrupt (RXSTPI) is raised and STALLRQ and STALLEDI are cleared by
hardware. The SETUP has to be ACKed.
This management simplifies the enumeration process management. If a command is not sup-
ported or contains an error, the firmware requests a STALL and can return to the main task,
waiting for the next SETUP request.
The retry mechanism has priority over the STALL handshake. A STALL handshake is sent if the
STALLRQ bit is set and if there is no retry required.
A SETUP request is always ACKed. When a new SETUP packet is received, the Received
SETUP interrupt (RXSTPI) is raised, but not the Received OUT Data interrupt (RXOUTI).
The FIFOCON and RWALL bits are irrelevant for control endpoints. The firmware shall therefore
never use them on these endpoints. When read, their value is always 0.
Control endpoints are managed using:
remote wake-up. This will automatically be done by the controller after 5 ms of inactivity on the
USB bus.
raised and SUSP is cleared by hardware.
interrupt (EORSM) is raised.
•the STALL Request bit (STALLRQ) to initiate a STALL request;
•the STALLed interrupt (STALLEDI) raised when a STALL handshake has been sent.
•the Received SETUP interrupt (RXSTPI) which is raised when a new SETUP packet is
received and which shall be cleared by firmware to acknowledge the packet and to free the
bank;
AT32UC3A
514
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