AT32UC3A0256 Atmel Corporation, AT32UC3A0256 Datasheet - Page 269

• Manufacturer Part Number: AT32UC3A0256
• Manufacturer: Atmel Corporation

Specifications of AT32UC3A0256

• Flash (kbytes): 256 Kbytes
• Pin Count: 144
• Max. Operating Frequency: 66 MHz
• Cpu: 32-bit AVR
• # Of Touch Channels: 32
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 109
• Ext Interrupts: 109
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device + OTG
• Spi: 6
• Twi (i2c): 1
• Uart: 4
• Ssc: 1
• Ethernet: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 384
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 16
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 64
• Self Program Memory: YES
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0-3.6 or (1.65-1.95+3.0-3.6)
• Operating Voltage (vcc): 3.0-3.6 or (1.65-1.95+3.0-3.6)
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 10
• Output Compare Channels: 16
• Input Capture Channels: 6
• Pwm Channels: 13
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

32058K AVR32-01/12
25.7.5
25.7.5.1
25.7.5.2
Frame Sync
Frame Sync Data
Frame Sync Edge Detection
The Transmitter and Receiver Frame Sync pins, TX_FRAME_SYNC and RX_FRAME_SYNC,
can be programmed to generate different kinds of frame synchronization signals. The Frame
Sync Output Selection (FSOS) field in the Receive Frame Mode Register (RFMR) and in the
Transmit Frame Mode Register (TFMR) are used to select the required waveform.
If a pulse waveform is selected, the Frame Sync Length (FSLEN) field in RFMR and TFMR pro-
grams the length of the pulse, from 1 bit time up to 16 bit time.
The periodicity of the Receive and Transmit Frame Sync pulse output can be programmed
through the Period Divider Selection (PERIOD) field in RCMR and TCMR.
Frame Sync Data transmits or receives a specific tag during the Frame Sync signal.
During the Frame Sync signal, the Receiver can sample the RX_DATA line and store the data in
the Receive Sync Holding Register and the transmitter can transfer Transmit Sync Holding Reg-
ister in the Shifter Register. The data length to be sampled/shifted out during the Frame Sync
signal is programmed by the FSLEN field in RFMR/TFMR.
Concerning the Receive Frame Sync Data operation, if the Frame Sync Length is equal to or
lower than the delay between the start event and the actual data reception, the data sampling
operation is performed in the Receive Sync Holding Register through the Receive Shift Register.
The Transmit Frame Sync Operation is performed by the transmitter only if the bit Frame Sync
Data Enable (FSDEN) in TFMR is set. If the Frame Sync length is equal to or lower than the
delay between the start event and the actual data transmission, the normal transmission has pri-
ority and the data contained in the Transmit Sync Holding Register is transferred in the Transmit
Register, then shifted out.
The Frame Sync Edge detection is programmed by the FSEDGE field in RFMR/TFMR. This sets
the corresponding flags RXSYN/TXSYN in the SSC Status Register (SR) on frame synchro
edge detection (signals RX_FRAME_SYNC/TX_FRAME_SYNC).
• Programmable low or high levels during data transfer are supported.
• Programmable high levels before the start of data transfers or toggling are also supported.
AT32UC3A
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