AT32UC3A0256 Atmel Corporation, AT32UC3A0256 Datasheet - Page 520

• Manufacturer Part Number: AT32UC3A0256
• Manufacturer: Atmel Corporation

Specifications of AT32UC3A0256

• Flash (kbytes): 256 Kbytes
• Pin Count: 144
• Max. Operating Frequency: 66 MHz
• Cpu: 32-bit AVR
• # Of Touch Channels: 32
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 109
• Ext Interrupts: 109
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device + OTG
• Spi: 6
• Twi (i2c): 1
• Uart: 4
• Ssc: 1
• Ethernet: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 384
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 16
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 64
• Self Program Memory: YES
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0-3.6 or (1.65-1.95+3.0-3.6)
• Operating Voltage (vcc): 3.0-3.6 or (1.65-1.95+3.0-3.6)
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 10
• Output Compare Channels: 16
• Input Capture Channels: 6
• Pwm Channels: 13
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

32058K AVR32-01/12
30.7.2.15
30.7.2.16
30.7.2.17
30.7.2.17.1 Global Interrupts
Interrupts
Overflow
CRC Error
An underflow can not occur during OUT stage on a CPU action, since the firmware may read
only if the bank is not empty (RXOUTI = 1 or RWALL = 1).
An underflow can also occur during OUT stage if the host sends a packet while the bank is
already full. Typically, the CPU is not fast enough. The packet is lost.
An underflow can not occur during IN stage on a CPU action, since the firmware may write only
if the bank is not full (TXINI = 1 or RWALL = 1).
This error exists for all endpoint types. It raises the Overflow interrupt (OVERFI), what triggers
an EPXINT interrupt if OVERFE = 1.
An overflow can occur during OUT stage if the host attempts to write into a bank that is too small
for the packet. The packet is acknowledged and the Received OUT Data interrupt (RXOUTI) is
raised as if no overflow had occurred. The bank is filled with all the first bytes of the packet that
fit in.
An overflow can not occur during IN stage on a CPU action, since the firmware may write only if
the bank is not full (TXINI = 1 or RWALL = 1).
This error exists only for isochronous OUT endpoints. It raises the CRC Error interrupt
(CRCERRI), what triggers an EPXINT interrupt if CRCERRE = 1.
A CRC error can occur during OUT stage if the USB controller detects a corrupted received
packet. The OUT packet is stored in the bank as if no CRC error had occurred (RXOUTI is
raised).
See the structure of the USB device interrupt system on
There are two kinds of device interrupts: processing, i.e. their generation is part of the normal
processing, and exception, i.e. errors (not related to CPU exceptions).
The processing device global interrupts are:
The exception device global interrupts are:
•the Suspend interrupt (SUSP);
•the Start of Frame interrupt (SOF) with no frame number CRC error (FNCERR = 0);
•the End of Reset interrupt (EORST);
•the Wake-Up interrupt (WAKEUP);
•the End of Resume interrupt (EORSM);
•the Upstream Resume interrupt (UPRSM);
•the Endpoint X interrupt (EPXINT);
•the DMA Channel X interrupt (DMAXINT).
•the Start of Frame interrupt (SOF) with a frame number CRC error (FNCERR = 1).
Figure 30-6 on page
AT32UC3A
504.
520