AT32UC3A0256 Atmel Corporation, AT32UC3A0256 Datasheet - Page 517

• Manufacturer Part Number: AT32UC3A0256
• Manufacturer: Atmel Corporation

Specifications of AT32UC3A0256

• Flash (kbytes): 256 Kbytes
• Pin Count: 144
• Max. Operating Frequency: 66 MHz
• Cpu: 32-bit AVR
• # Of Touch Channels: 32
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 109
• Ext Interrupts: 109
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device + OTG
• Spi: 6
• Twi (i2c): 1
• Uart: 4
• Ssc: 1
• Ethernet: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 384
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 16
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 64
• Self Program Memory: YES
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0-3.6 or (1.65-1.95+3.0-3.6)
• Operating Voltage (vcc): 3.0-3.6 or (1.65-1.95+3.0-3.6)
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 10
• Output Compare Channels: 16
• Input Capture Channels: 6
• Pwm Channels: 13
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

32058K AVR32-01/12
Figure 30-18. Example of an IN Endpoint with 2 Data Banks
30.7.2.12.2 Detailed Description
TXINI
FIFOCON
SW
write data to CPU
The data is written by the firmware, following the next flow:
If the endpoint uses several banks, the current one can be written by the firmware while the pre-
vious one is being read by the host. Then, when the firmware clears FIFOCON, the following
bank may already be free and TXINI is set immediately.
An “Abort” stage can be produced when a zero-length OUT packet is received during an IN
stage of a control or isochronous IN transaction. The KILLBK bit is used to kill the last written
bank. The best way to manage this abort is to apply the algorithm represented on
•when the bank is empty, TXINI and FIFOCON are set, what triggers an EPXINT interrupt if
•the firmware acknowledges the interrupt by clearing TXINI;
•the firmware writes the data into the current bank by using the USB Pipe/Endpoint X FIFO
•the firmware allows the controller to send the bank and switches to the next bank (if any) by
BANK 0
TXINE = 1;
Data register (USB_FIFOX_DATA), until all the data frame is written or the bank is full (in
which case RWALL is cleared by hardware and BYCT reaches the endpoint size);
clearing FIFOCON.
SW
IN
SW
write data to CPU
BANK 1
(bank 0)
DATA
SW
HW
ACK
SW
write data to CPU
IN
BANK0
(bank 1)
DATA
AT32UC3A
ACK
Figure
30-19.
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