AT32UC3A464S Atmel Corporation, AT32UC3A464S Datasheet - Page 701

• Manufacturer Part Number: AT32UC3A464S
• Manufacturer: Atmel Corporation

Specifications of AT32UC3A464S

• Flash (kbytes): 64 Kbytes
• Pin Count: 100
• Max. Operating Frequency: 66 MHz
• Cpu: 32-bit AVR
• Hardware Qtouch Acquisition: No
• Usb Transceiver: 1
• Usb Speed: Hi-Speed
• Usb Interface: Device + OTG
• Spi: 6
• Twi (i2c): 2
• Uart: 4
• Ssc: 1
• Sd / Emmc: 2
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: AES
• Sram (kbytes): 128
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0 to 3.6
• Operating Voltage (vcc): 3.0 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

• NAKOUTE: NAKed OUT Interrupt Enable
• HBISOINERRE: High Bandwidth Isochronous IN Error Interrupt Enable
• RXSTPE: Received SETUP Interrupt Enable
• UNDERFE: Underflow Interrupt Enable
• RXOUTE: Received OUT Data Interrupt Enable
• TXINE: Transmitted IN Data Interrupt Enable
32072G–11/2011
This bit is cleared when the HBISOFLUSHEC bit disable the HBISOFLUSHI interrupt.
Look at the UFEATURES register to know if the high-bandwidth isochronous feature is supported by the device.
This bit is set when the NAKOUTES bit is written to one. This will enable the NAKed OUT interrupt (NAKOUTI).
This bit is cleared when the NAKOUTEC bit is written to one. This will disable the NAKed OUT interrupt (NAKOUTI).
This bit is set when the HBISOINERRES bit is written to one. This will enable the HBISOINERRI interrupt.
This bit is cleared when the HBISOINERREC bit disable the HBISOINERRI interrupt.
Look at the UFEATURES register to know if the high-bandwidth isochronous feature is supported by the device.
This bit is set when the RXSTPES bit is written to one. This will enable the Received SETUP interrupt (RXSTPI).
This bit is cleared when the RXSTPEC bit is written to one. This will disable the Received SETUP interrupt (RXSTPI).
This bit is set when the UNDERFES bit is written to one. This will enable the Underflow interrupt (UNDERFI).
This bit is cleared when the UNDERFEC bit is written to one. This will disable the Underflow interrupt (UNDERFI).
This bit is set when the RXOUTES bit is written to one. This will enable the Received OUT Data interrupt (RXOUT).
This bit is cleared when the RXOUTEC bit is written to one. This will disable the Received OUT Data interrupt (RXOUT).
This bit is set when the TXINES bit is written to one. This will enable the Transmitted IN Data interrupt (TXINI).
This bit is cleared when the TXINEC bit is written to one. This will disable the Transmitted IN Data interrupt (TXINI).
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