AT32UC3A464S Atmel Corporation, AT32UC3A464S Datasheet - Page 787

• Manufacturer Part Number: AT32UC3A464S
• Manufacturer: Atmel Corporation

Specifications of AT32UC3A464S

• Flash (kbytes): 64 Kbytes
• Pin Count: 100
• Max. Operating Frequency: 66 MHz
• Cpu: 32-bit AVR
• Hardware Qtouch Acquisition: No
• Usb Transceiver: 1
• Usb Speed: Hi-Speed
• Usb Interface: Device + OTG
• Spi: 6
• Twi (i2c): 2
• Uart: 4
• Ssc: 1
• Sd / Emmc: 2
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: AES
• Sram (kbytes): 128
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0 to 3.6
• Operating Voltage (vcc): 3.0 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

Figure 28-3. GOVRE and OVREn Flag Behavior
32072G–11/2011
OVRE0(SR)
GOVRE(SR)
DRDY(ASR)
CH0(CHSR)
CH1(CHSR)
TRIGGER
EOC0(SR)
EOC1(SR)
LCDR
CRD0
CRD1
Undefined Data
Undefined Data
If the CDR register is not read before further incoming data is converted, the corresponding
Overrun Error bit in the SR register (SR.OVREn) is set.
In the same way, new data converted when DRDY is high sets the General Overrun Error bit in
the SR register (SR.GOVRE).
The OVREn and GOVRE bits are automatically cleared when the SR register is read.
Warning: If the corresponding channel is disabled during a conversion or if it is disabled and
then reenabled during a conversion, its associated data and its corresponding EOC and OVRE
flags in SR are unpredictable.
Conversion
Undefined Data
Conversion
Data A
Data A
Data B
Conversion
Data B
Data C
Data C
Read CDR1
Read CDR0
Read SR
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