AT32UC3B0128 Atmel Corporation, AT32UC3B0128 Datasheet - Page 202
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AT32UC3B0128
Manufacturer Part Number
AT32UC3B0128
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT32UC3A0128.pdf
(377 pages)
2.AT32UC3A0128.pdf
(33 pages)
3.AT32UC3A0128.pdf
(159 pages)
4.AT32UC3B0128.pdf
(684 pages)
5.AT32UC3B0128.pdf
(107 pages)
Specifications of AT32UC3B0128
Flash (kbytes)
128 Kbytes
Pin Count
64
Max. Operating Frequency
60 MHz
Cpu
32-bit AVR
# Of Touch Channels
32
Hardware Qtouch Acquisition
No
Max I/o Pins
44
Ext Interrupts
44
Usb Transceiver
1
Usb Speed
Full Speed
Usb Interface
Device + OTG
Spi
4
Twi (i2c)
1
Uart
3
Ssc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
384
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
32
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
3.0-3.6 or (1.65-1.95+3.0-3.6)
Operating Voltage (vcc)
3.0-3.6 or (1.65-1.95+3.0-3.6)
Fpu
No
Mpu / Mmu
Yes / No
Timers
10
Output Compare Channels
16
Input Capture Channels
6
Pwm Channels
13
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
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18.7.3.5
18.7.3.6
18.7.3.7
32059L–AVR32–01/2012
Peripheral Selection
Peripheral Chip Select Decoding
Peripheral Deselection
The serial peripherals are selected through the assertion of the NPCS0 to NPCS3 signals. By
default, all the NPCS signals are high before and after each transfer.
The peripheral selection can be performed in two different ways:
Fixed Peripheral Select is activated by writing the PS bit to zero in MR (Mode Register). In this
case, the current peripheral is defined by the PCS field in MR and the PCS field in the TDR has
no effect.
Variable Peripheral Select is activated by setting PS bit to one. The PCS field in TDR is used to
select the current peripheral. This means that the peripheral selection can be defined for each
new data.
The Fixed Peripheral Selection allows buffer transfers with a single peripheral. Using the Periph-
eral DMA Controller is an optimal means, as the size of the data transfer between the memory
and the SPI is either 8 bits or 16 bits. However, changing the peripheral selection requires the
Mode Register to be reprogrammed.
The Variable Peripheral Selection allows buffer transfers with multiple peripherals without repro-
gramming the Mode Register. Data written in TDR is 32 bits wide and defines the real data to be
transmitted and the peripheral it is destined to. Using the Peripheral DMA Controller in this mode
requires 32-bit wide buffers, with the data in the LSBs and the PCS and LASTXFER fields in the
MSBs, however the SPI still controls the number of bits (8 to16) to be transferred through MISO
and MOSI lines with the chip select configuration registers. This is not the optimal means in term
of memory size for the buffers, but it provides a very effective means to exchange data with sev-
eral peripherals without any intervention of the processor.
The user can program the SPI to operate with up to 15 peripherals by decoding the four Chip
Select lines, NPCS0 to NPCS3 with an external logic. This can be enabled by writing the PCS-
DEC bit at 1 in the Mode Register (MR).
When operating without decoding, the SPI makes sure that in any case only one chip select line
is activated, i.e. driven low at a time. If two bits are defined low in a PCS field, only the lowest
numbered chip select is driven low.
When operating with decoding, the SPI directly outputs the value defined by the PCS field of
either the Mode Register or the Transmit Data Register (depending on PS).
As the SPI sets a default value of 0xF on the chip select lines (i.e. all chip select lines at 1) when
not processing any transfer, only 15 peripherals can be decoded.
The SPI has only four Chip Select Registers, not 15. As a result, when decoding is activated,
each chip select defines the characteristics of up to four peripherals. As an example, CRS0
defines the characteristics of the externally decoded peripherals 0 to 3, corresponding to the
PCS values 0x0 to 0x3. Thus, the user has to make sure to connect compatible peripherals on
the decoded chip select lines 0 to 3, 4 to 7, 8 to 11 and 12 to 14.
When operating normally, as soon as the transfer of the last data written in TDR is completed,
the NPCS lines all rise. This might lead to runtime error if the processor is too long in responding
• Fixed Peripheral Select: SPI exchanges data with only one peripheral
• Variable Peripheral Select: Data can be exchanged with more than one peripheral
202
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