AT32UC3B0128 Atmel Corporation, AT32UC3B0128 Datasheet - Page 252
AT32UC3B0128
Manufacturer Part Number
AT32UC3B0128
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT32UC3A0128.pdf
(377 pages)
2.AT32UC3A0128.pdf
(33 pages)
3.AT32UC3A0128.pdf
(159 pages)
4.AT32UC3B0128.pdf
(684 pages)
5.AT32UC3B0128.pdf
(107 pages)
Specifications of AT32UC3B0128
Flash (kbytes)
128 Kbytes
Pin Count
64
Max. Operating Frequency
60 MHz
Cpu
32-bit AVR
# Of Touch Channels
32
Hardware Qtouch Acquisition
No
Max I/o Pins
44
Ext Interrupts
44
Usb Transceiver
1
Usb Speed
Full Speed
Usb Interface
Device + OTG
Spi
4
Twi (i2c)
1
Uart
3
Ssc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
384
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
32
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
3.0-3.6 or (1.65-1.95+3.0-3.6)
Operating Voltage (vcc)
3.0-3.6 or (1.65-1.95+3.0-3.6)
Fpu
No
Mpu / Mmu
Yes / No
Timers
10
Output Compare Channels
16
Input Capture Channels
6
Pwm Channels
13
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
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19.14.6
Name:
Access:
Offset:
Reset Value: 0x0000F009
• EOSACC: End Of Slave Access (clear on read)
• SCLWS: Clock Wait State (automatically set / reset)
• ARBLST: Arbitration Lost (clear on read)
• NACK: Not Acknowledged (clear on read)
• OVRE: Overrun Error (clear on read)
• GACC: General Call Access (clear on read)
32059L–AVR32–01/2012
31
23
15
–
–
–
7
–
This bit is only used in Slave mode.
0 = A slave access is being performing.
1 = The Slave Access is finished. End Of Slave Access is automatically set as soon as SVACC is reset.
EOSACC behavior can be seen in
This bit is only used in Slave mode.
0 = The clock is not stretched.
1 = The clock is stretched. THR / RHR buffer is not filled / emptied before the emission / reception of a new character.
SCLWS behavior can be seen in
This bit is only used in Master mode.
0 = Arbitration won.
1 = Arbitration lost. Another master of the TWI bus has won the multi-master arbitration. TXCOMP is set at the same time.
NACK used in Master mode:
0 = Each data byte has been correctly received by the far-end side TWI slave component.
1 = A data byte has not been acknowledged by the slave component. Set at the same time as TXCOMP.
NACK used in Slave Read mode:
0 = Each data byte has been correctly received by the Master.
1 = In read mode, a data byte has not been acknowledged by the Master. When NACK is set the programmer must not fill THR
even if TXRDY is set, because it means that the Master will stop the data transfer or re initiate it.
Note that in Slave Write mode all data are acknowledged by the TWI.
This bit is only used in Slave mode.
0 = RHR has not been loaded while RXRDY was set
1 = RHR has been loaded while RXRDY was set. Reset by read in SR when TXCOMP is set.
This bit is only used in Slave mode.
0 = No General Call has been detected.
Status Register
SR
Read-only
0x20
OVRE
30
22
14
–
–
–
6
GACC
29
21
13
–
–
–
5
Figure 19-27 on page 241
Figure 19-29 on page 243
SVACC
28
20
12
–
–
–
4
and
and
EOSACC
SVREAD
Figure 19-28 on page
Figure 19-30 on page 243
27
19
11
–
–
3
SCLWS
TXRDY
26
18
10
–
–
2
242.
ARBLST
RXRDY
25
17
–
–
9
1
TXCOMP
NACK
24
16
–
–
8
0
252
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