AT32UC3B0128 Atmel Corporation, AT32UC3B0128 Datasheet - Page 222
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AT32UC3B0128
Manufacturer Part Number
AT32UC3B0128
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT32UC3A0128.pdf
(377 pages)
2.AT32UC3A0128.pdf
(33 pages)
3.AT32UC3A0128.pdf
(159 pages)
4.AT32UC3B0128.pdf
(684 pages)
5.AT32UC3B0128.pdf
(107 pages)
Specifications of AT32UC3B0128
Flash (kbytes)
128 Kbytes
Pin Count
64
Max. Operating Frequency
60 MHz
Cpu
32-bit AVR
# Of Touch Channels
32
Hardware Qtouch Acquisition
No
Max I/o Pins
44
Ext Interrupts
44
Usb Transceiver
1
Usb Speed
Full Speed
Usb Interface
Device + OTG
Spi
4
Twi (i2c)
1
Uart
3
Ssc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
384
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
32
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
3.0-3.6 or (1.65-1.95+3.0-3.6)
Operating Voltage (vcc)
3.0-3.6 or (1.65-1.95+3.0-3.6)
Fpu
No
Mpu / Mmu
Yes / No
Timers
10
Output Compare Channels
16
Input Capture Channels
6
Pwm Channels
13
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
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19.10 Master Mode
19.10.1
19.10.2
Figure 19-5. Master Mode Typical Application Block Diagram
19.10.3
19.10.4
19.10.5
32059L–AVR32–01/2012
Definition
Application Block Diagram
Programming Master Mode
Master Mode Clock Timing
Master Transmitter Mode
Rp: Pull up value as given by the I²C Standard
Host with
Interface
TWI
The Master is the device which starts a transfer, generates a clock and stops it.
The following registers have to be programmed before entering Master mode:
The TWI module monitors the state of the TWCK line as required by the I²C specification. The
counter that determines the TWCK T
is detected by the module on TWCK, not when the module begins releasing or driving the TWCK
line. Thus, the CWGR.CHDIV and CLDIV fields do not alone determine the overall TWCK
period; they merely determine the T
(T
tion and synchronization delay of TWCK from the pin back into the TWI module. The TWI
module does not attempt to compensate for these delays, so the overall TWI clock period is
given by T
After the master initiates a Start condition when writing into the Transmit Holding Register, THR,
it sends a 7-bit slave address, configured in the Master Mode register (DADR in MMR), to notify
the slave device. The bit following the slave address indicates the transfer direction, 0 in this
case (MREAD = 0 in MMR).
TWD
TWCK
1. DADR (+ IADRSZ + IADR if a 10 bit device is addressed): The device address is used
2. CKDIV + CHDIV + CLDIV: Determines clock waveform T
3. SVDIS: Disable the slave mode.
4. MSEN: Enable the master mode.
rise
Serial EEPROM
and T
to access slave devices in read or write mode.
Atmel TWI
Slave 1
high
fall
) are determined by the external circuitry on the TWCK pin as well as the propaga-
+T
fall
+T
low
+T
I²C RTC
Slave 2
rise
.
high
high
Controller
I²C LCD
Slave 3
or T
and T
low
low
duration is started whenever a high or low level
components, whereas the rise and fall times
I²C Temp.
Slave 4
Sensor
Rp
high
and T
Rp
low
.
VDD
222
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