AT32UC3B0128 Atmel Corporation, AT32UC3B0128 Datasheet - Page 388
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AT32UC3B0128
Manufacturer Part Number
AT32UC3B0128
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT32UC3A0128.pdf
(377 pages)
2.AT32UC3A0128.pdf
(33 pages)
3.AT32UC3A0128.pdf
(159 pages)
4.AT32UC3B0128.pdf
(684 pages)
5.AT32UC3B0128.pdf
(107 pages)
Specifications of AT32UC3B0128
Flash (kbytes)
128 Kbytes
Pin Count
64
Max. Operating Frequency
60 MHz
Cpu
32-bit AVR
# Of Touch Channels
32
Hardware Qtouch Acquisition
No
Max I/o Pins
44
Ext Interrupts
44
Usb Transceiver
1
Usb Speed
Full Speed
Usb Interface
Device + OTG
Spi
4
Twi (i2c)
1
Uart
3
Ssc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
384
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
32
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
3.0-3.6 or (1.65-1.95+3.0-3.6)
Operating Voltage (vcc)
3.0-3.6 or (1.65-1.95+3.0-3.6)
Fpu
No
Mpu / Mmu
Yes / No
Timers
10
Output Compare Channels
16
Input Capture Channels
6
Pwm Channels
13
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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AT32UC3B0128-A2UT
Manufacturer:
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Quantity:
150
Company:
Part Number:
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Manufacturer:
ATMEL
Quantity:
9 500
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Part Number:
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ATMEL
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1 400
Part Number:
AT32UC3B0128-U
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
Part Number:
AT32UC3B0128-Z2UT
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
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22.7.4
22.7.4.1
32059L–AVR32–01/2012
USB DMA Operation
Introduction
USB packets of any length may be transferred when required by the USBB. These transfers
always feature sequential addressing. These two characteristics mean that in case of high
USBB throughput, both HSB ports will benefit from “incrementing burst of unspecified length”
since the average access latency of HSB slaves can then be reduced.
The DMA uses word “incrementing burst of unspecified length” of up to 256 beats for both data
transfers and channel descriptor loading. A burst may last on the HSB busses for the duration of
a whole USB packet transfer, unless otherwise broken by the HSB arbitration or the HSB 1kbyte
boundary crossing.
Packet data HSB bursts may be locked on a DMA buffer basis for drastic overall HSB bus band-
width performance boost with paged memories. This is because these memories row (or bank)
changes, which are very clock-cycle consuming, will then likely not occur or occur once instead
of dozens of times during a single big USB packet DMA transfer in case other HSB masters
address the memory. This means up to 128 words single cycle unbroken HSB bursts for bulk
pipes/endpoints and 256 words single cycle unbroken bursts for isochronous pipes/endpoints.
This maximal burst length is then controlled by the lowest programmed USB pipe/endpoint size
(PSIZE/EPSIZE) and the Channel Byte Length (CHBYTELENGTH) field in the Device DMA
Channel n Control (UDDMAnCONTROL) register.
The USBB average throughput may be up to nearly 12 Mbit/s. Its average access latency
decreases as burst length increases due to the zero wait-state side effect of unchanged
pipe/endpoint. Word access allows reducing the HSB bandwidth required for the USB by four
compared to native byte access. If at least 0 wait-state word burst capability is also provided by
the other DMA HSB bus slaves, each of both DMA HSB busses need less than 1.1% bandwidth
allocation for full USB bandwidth usage at 33MHz, and less than 0.6% at 66MHz.
388
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