AT32UC3B0128 Atmel Corporation, AT32UC3B0128 Datasheet - Page 428
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AT32UC3B0128
Manufacturer Part Number
AT32UC3B0128
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT32UC3A0128.pdf
(377 pages)
2.AT32UC3A0128.pdf
(33 pages)
3.AT32UC3A0128.pdf
(159 pages)
4.AT32UC3B0128.pdf
(684 pages)
5.AT32UC3B0128.pdf
(107 pages)
Specifications of AT32UC3B0128
Flash (kbytes)
128 Kbytes
Pin Count
64
Max. Operating Frequency
60 MHz
Cpu
32-bit AVR
# Of Touch Channels
32
Hardware Qtouch Acquisition
No
Max I/o Pins
44
Ext Interrupts
44
Usb Transceiver
1
Usb Speed
Full Speed
Usb Interface
Device + OTG
Spi
4
Twi (i2c)
1
Uart
3
Ssc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
384
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
32
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
3.0-3.6 or (1.65-1.95+3.0-3.6)
Operating Voltage (vcc)
3.0-3.6 or (1.65-1.95+3.0-3.6)
Fpu
No
Mpu / Mmu
Yes / No
Timers
10
Output Compare Channels
16
Input Capture Channels
6
Pwm Channels
13
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
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• STALLEDI: STALLed Interrupt
• CRCERRI: CRC Error Interrupt
• OVERFI: Overflow Interrupt
• NAKINI: NAKed IN Interrupt
• NAKOUTI: NAKed OUT Interrupt
• UNDERFI: Underflow Interrupt
• RXSTPI: Received SETUP Interrupt
• RXOUTI: Received OUT Data Interrupt
32059L–AVR32–01/2012
This bit is set for non-control IN endpoints, a short packet is transmitted upon ending a DMA transfer, thus signaling an end of
isochronous frame or a bulk or interrupt end of transfer, this only if the End of DMA Buffer Output Enable (DMAENDEN) bit and
the Automatic Switch (AUTOSW) bit are written to one.
This triggers an EPnINT interrupt if SHORTPACKETE is one.
This bit is cleared when the SHORTPACKETC bit is written to one. This will acknowledge the interrupt.
This bit is set to signal that a STALL handshake has been sent. To do that, the software has to set the STALLRQ bit (by writing
a one to the STALLRQS bit). This triggers an EPnINT interrupt if STALLEDE is one.
This bit is cleared when the STALLEDIC bit is written to one. This will acknowledge the interrupt.
This bit is set to signal that a CRC error has been detected in an isochronous OUT endpoint. The OUT packet is stored in the
bank as if no CRC error had occurred. This triggers an EPnINT interrupt if CRCERRE is one.
This bit is cleared when the CRCERRIC bit is written to one. This will acknowledge the interrupt.
This bit is set when an overflow error occurs. This triggers an EPnINT interrupt if OVERFE is one.
For all endpoint types, an overflow can occur during OUT stage if the host attempts to write into a bank that is too small for the
packet. The packet is acknowledged and the RXOUTI bit is set as if no overflow had occurred. The bank is filled with all the first
bytes of the packet that fit in.
This bit is cleared when the OVERFIC bit is written to one. This will acknowledge the interrupt.
This bit is set when a NAK handshake has been sent in response to an IN request from the host. This triggers an EPnINT
interrupt if NAKINE is one.
This bit is cleared when the NAKINIC bit is written to one. This will acknowledge the interrupt.
This bit is set when a NAK handshake has been sent in response to an OUT request from the host. This triggers an EPnINT
interrupt if NAKOUTE is one.
This bit is cleared when the NAKOUTIC bit is written to one. This will acknowledge the interrupt.
This bit is set, for isochronous IN/OUT endpoints, when an underflow error occurs. This triggers an EPnINT interrupt if
UNDERFE is one.
An underflow can occur during IN stage if the host attempts to read from an empty bank. A zero-length packet is then
automatically sent by the USBB.
An underflow can also occur during OUT stage if the host sends a packet while the bank is already full. Typically, the CPU is not
fast enough. The packet is lost.
Shall be cleared by writing a one to the UNDERFIC bit. This will acknowledge the interrupt.
This bit is inactive (cleared) for bulk and interrupt IN/OUT endpoints and it means RXSTPI for control endpoints.
This bit is set, for control endpoints, to signal that the current bank contains a new valid SETUP packet. This triggers an EPnINT
interrupt if RXSTPE is one.
Shall be cleared by writing a one to the RXSTPIC bit. This will acknowledge the interrupt and free the bank.
This bit is inactive (cleared) for bulk and interrupt IN/OUT endpoints and it means UNDERFI for isochronous IN/OUT endpoints.
This bit is set, for control endpoints, when the current bank contains a bulk OUT packet (data or status stage). This triggers an
EPnINT interrupt if RXOUTE is one.
Shall be cleared for control end points, by writing a one to the RXOUTIC bit. This will acknowledge the interrupt and free the
bank.
This bit is set for isochronous, bulk and, interrupt OUT endpoints, at the same time as FIFOCON when the current bank is full.
This triggers an EPnINT interrupt if RXOUTE is one.
428
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