AT32UC3C1512C Atmel Corporation, AT32UC3C1512C Datasheet - Page 1054

• Manufacturer Part Number: AT32UC3C1512C
• Manufacturer: Atmel Corporation

Specifications of AT32UC3C1512C

• Flash (kbytes): 512 Kbytes
• Pin Count: 100
• Max. Operating Frequency: 66 MHz
• Cpu: 32-bit AVR
• # Of Touch Channels: 32
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 81
• Ext Interrupts: 100
• Usb Transceiver: 1
• Quadrature Decoder Channels: 2
• Usb Speed: Full Speed
• Usb Interface: Device + OTG
• Spi: 7
• Twi (i2c): 3
• Uart: 5
• Can: 2
• Lin: 5
• Ssc: 1
• Ethernet: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 16
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 4
• Resistive Touch Screen: No
• Dac Channels: 4
• Dac Resolution (bits): 12
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 68
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0 to 3.6 or 4.5 to 5.5
• Operating Voltage (vcc): 3.0 to 3.6 or 4.5 to 5.5
• Fpu: Yes
• Mpu / Mmu: Yes / No
• Timers: 6
• Output Compare Channels: 22
• Input Capture Channels: 12
• Pwm Channels: 19
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

34.6.3
32117C–AVR-08/11
Interrupts
Figure 34-7. Timer Block Diagram
The user can set the timer count direction by writing to the CF.TSDIR bit. The counting direction
is taken into account when a trigger occurs. The counting direction is shown in SR.CNTDIR.
The user has to set the initial direction of counting by writing to CF.TSDIR. When the timer is
triggered, i.e. each time a toggle direction event occurs, the counter changes counting direction.
If the counter reaches 0, it will be stuck at 0 as long as the counting direction is down.
The QDEC has one interrupt request line connected to the interrupt controller. The sources of
this interrupt are:
• The QEPI interrupt to detect the index signal.
• The CMP interrupt to detect a compare match.
• The CAP interrupt to detect that the QDEC counter value has been saved in the CAP register
• The OVR interrupt to detect that a capture event was received without the CAP register
• The PCRO interrupt to detect a roll-over of the position counter. In Timer/Counter mode, the
toggle direction event
due to the capture event.
having been read since the last capture event. In OCD mode, reading the CAP register does
not clear the memory of the last capture event.
roll over occurs when (PC = 0xFFFF and RC != RCTOP), when PC = TOP.PCTOP or when
RC = RCTOP.
Clock Control
CF.TSDIR
CF.UPD
up/down
control
GCLK_QDEC
CLK_QDEC_INT
compare event
DIR
CMP
trigger event
CNT
TOP
CAP
AT32UC3C
capture event
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