AT32UC3C1512C Atmel Corporation, AT32UC3C1512C Datasheet - Page 408

• Manufacturer Part Number: AT32UC3C1512C
• Manufacturer: Atmel Corporation

Specifications of AT32UC3C1512C

• Flash (kbytes): 512 Kbytes
• Pin Count: 100
• Max. Operating Frequency: 66 MHz
• Cpu: 32-bit AVR
• # Of Touch Channels: 32
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 81
• Ext Interrupts: 100
• Usb Transceiver: 1
• Quadrature Decoder Channels: 2
• Usb Speed: Full Speed
• Usb Interface: Device + OTG
• Spi: 7
• Twi (i2c): 3
• Uart: 5
• Can: 2
• Lin: 5
• Ssc: 1
• Ethernet: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 16
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 4
• Resistive Touch Screen: No
• Dac Channels: 4
• Dac Resolution (bits): 12
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 68
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0 to 3.6 or 4.5 to 5.5
• Operating Voltage (vcc): 3.0 to 3.6 or 4.5 to 5.5
• Fpu: Yes
• Mpu / Mmu: Yes / No
• Timers: 6
• Output Compare Channels: 22
• Input Capture Channels: 12
• Pwm Channels: 19
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

20.8
32117C–AVR-08/11
Module Configuration
The specific configuration for the PDCA instance is listed in the following tables.
Table 20-6.
Table 20-7.
Table 20-8.
The table below defines the valid Peripheral Identifiers (PIDs). The direction is specified as
observed from the memory, so RX means transfers from peripheral to memory and TX means
from memory to peripheral.
Table 20-9.
Features
Number of channels
Number of performance monitors
Module name
PDCA
Register
PSRn
VERSION
PID
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Direction
RX
RX
RX
RX
RX
RX
RX
RX
RX
RX
RX
RX
RX
TX
TX
TX
TX
PDCA Configuration
Module Clock Name
Register Reset Values
Peripheral Identity Values
Reset Value
n
0x123
Clock name
CLK_PDCA_HSB
CLK_PDCA_PB
Peripheral Instance
ADCIFA
ADCIFA
USART0
USART1
USART2
USART3
TWIM0
TWIM1
TWIS0
TWIS1
SPI0
SPI1
AW
USART0
USART1
USART2
USART3
PDCA
16
1
Description
HSB clock
Peripheral Bus clock from the PBC clock domain
Peripheral Register
LCV0
LCV1
RHR
RHR
RHR
RHR
RHR
RHR
RHR
RHR
RDR
RDR
RHR
THR
THR
THR
THR
AT32UC3C
408