AT32UC3C1512C Atmel Corporation, AT32UC3C1512C Datasheet - Page 1222

• Manufacturer Part Number: AT32UC3C1512C
• Manufacturer: Atmel Corporation

Specifications of AT32UC3C1512C

• Flash (kbytes): 512 Kbytes
• Pin Count: 100
• Max. Operating Frequency: 66 MHz
• Cpu: 32-bit AVR
• # Of Touch Channels: 32
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 81
• Ext Interrupts: 100
• Usb Transceiver: 1
• Quadrature Decoder Channels: 2
• Usb Speed: Full Speed
• Usb Interface: Device + OTG
• Spi: 7
• Twi (i2c): 3
• Uart: 5
• Can: 2
• Lin: 5
• Ssc: 1
• Ethernet: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 16
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 4
• Resistive Touch Screen: No
• Dac Channels: 4
• Dac Resolution (bits): 12
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 68
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0 to 3.6 or 4.5 to 5.5
• Operating Voltage (vcc): 3.0 to 3.6 or 4.5 to 5.5
• Fpu: Yes
• Mpu / Mmu: Yes / No
• Timers: 6
• Output Compare Channels: 22
• Input Capture Channels: 12
• Pwm Channels: 19
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

39.5.3.5
32117C–AVR-08/11
MEMORY_BLOCK_ACCESS
Table 39-20. MEMORY_WORD_ACCESS Details (Continued)
This instruction allows access to the entire SAB data area. Up to 32 bits of data is accessed at a
time, while the address is sequentially incremented from the previously used address.
In this mode, the SAB address, size, and access direction is not provided with each access.
Instead, the previous address is auto-incremented depending on the specified size and the pre-
v i o u s o p e r a t i o n r e p e a t e d . T h e a d d r e s s m u s t b e s e t u p i n a d v a n c e w i t h
MEMORY_SIZE_ACCESS or MEMORY_WORD_ACCESS. It is allowed, but not required, to
shift data after shifting the address.
This instruction is primarily intended to speed up large quantities of sequential word accesses. It
is possible to use it also for byte and halfword accesses, but the overhead in this is case much
larger as 32 bits must still be shifted for each access.
The following sequence should be used:
For write operations, 32 data bits must be provided, or the result will be undefined. For read
operations, shifting may be terminated once the required number of bits have been acquired.
Table 39-21. MEMORY_BLOCK_ACCESS Details
Instructions
DR output value (Address phase)
DR output value (Data read phase)
DR output value (Data write phase)
Instructions
IR input value
IR output value
DR Size
DR input value (Data read phase)
1. Use the MEMORY_SIZE_ACCESS or MEMORY_WORD_ACCESS to read or write the
2. Return to Run-Test/Idle.
3. Select the IR Scan path.
4. In Capture-IR: The IR output value is latched into the shift register.
5. In Shift-IR: The instruction register is shifted by the TCK input.
6. Return to Run-Test/Idle.
7. Select the DR Scan path. The address will now have incremented by 1, 2, or 4 (corre-
8. In Shift-DR: For a read operation, scan out the contents of the next addressed location.
9. Go to Update-DR.
10. If the block access is not complete, return to Select-DR Scan and repeat the access.
11. If the block access is complete, return to Run-Test/Idle.
first location.
sponding to the next byte, halfword, or word location).
For a write operation, scan in the new contents of the next addressed location.
Details
xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xeb
xeb dddddddd dddddddd dddddddd dddddddd
xxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxeb
Details
10010 (0x12)
peb01
34 bits
xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xx
AT32UC3C
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