AT32UC3C1512C Atmel Corporation, AT32UC3C1512C Datasheet - Page 410

• Manufacturer Part Number: AT32UC3C1512C
• Manufacturer: Atmel Corporation

Specifications of AT32UC3C1512C

• Flash (kbytes): 512 Kbytes
• Pin Count: 100
• Max. Operating Frequency: 66 MHz
• Cpu: 32-bit AVR
• # Of Touch Channels: 32
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 81
• Ext Interrupts: 100
• Usb Transceiver: 1
• Quadrature Decoder Channels: 2
• Usb Speed: Full Speed
• Usb Interface: Device + OTG
• Spi: 7
• Twi (i2c): 3
• Uart: 5
• Can: 2
• Lin: 5
• Ssc: 1
• Ethernet: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 16
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 4
• Resistive Touch Screen: No
• Dac Channels: 4
• Dac Resolution (bits): 12
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 68
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0 to 3.6 or 4.5 to 5.5
• Operating Voltage (vcc): 3.0 to 3.6 or 4.5 to 5.5
• Fpu: Yes
• Mpu / Mmu: Yes / No
• Timers: 6
• Output Compare Channels: 22
• Input Capture Channels: 12
• Pwm Channels: 19
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

21. Memory DMA Controller (MDMA)
21.1
21.2
21.3
21.3.1
21.3.2
21.3.3
32117C–AVR-08/11
Features
Overview
Product Dependencies
Power Management
Clocks
Interrupts
Rev 1.0.1.1
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The purpose of the MDMA is to perform memory-to-memory transfers. For peripheral-to-memory
transfers, the Peripheral DMA Controller should be used instead.
The MDMA has two HSB master interfaces. One interface is dedicated to reading data while the
other is dedicated to writing. The MDMA is configured through a Peripheral Bus (PB) interface.
A DMA transfer on a channel can be started manually by writing the MDMA configuration regis-
ters for that channel. This transfer mode is referred to as Single Transfer Mode.
MDMA channels can also be controlled by a descriptor list in memory. The descriptor list con-
tains all information needed to control a transfer. Once a transfer has been completed, the
MDMA automatically reads the next descriptor, and if this descriptor is valid, starts the next DMA
transfer. This transfer mode is referred to Descriptor Mode.
In order to use this module, other parts of the system must be configured correctly, as described
below.
If the CPU enters a sleep mode that disables clocks used by the MDMA, the MDMA will stop
functioning and resume operation after the system wakes up from sleep mode.
The MDMA has two bus clocks connected: One High Speed Bus clock (CLK_MDMA_HSB) and
one Peripheral Bus clock (CLK_MDMA_PB). These clocks are generated by the Power Man-
ager. Both clocks are enabled at reset, and can be disabled in the Power Manager. The user
has to ensure that CLK_MDMA_HSB is not turned off while performing MDMA transfers. Failing
to do so may deadlock the HSB.
The MDMA interrupt request lines are connected to the interrupt controller. Using the MDMA
interrupts requires the interrupt controller to be programmed first.
1-4 DMA channels, depending on implementation
Chained (descriptor-list controlled) or unchained (single) transfers
Descriptor read and writeback support
Descriptors are placed in circular buffers of programmable length
Programmable fixed or round-robin priority between channels
Programmable burst length (1, 4, 8, or 16-beat)
Byte/halfword/word transfers
Optional endianess-conversion on transferred data
Interrupt on transfer complete
AT32UC3C
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