AT32UC3L064 Atmel Corporation, AT32UC3L064 Datasheet - Page 93

• Manufacturer Part Number: AT32UC3L064
• Manufacturer: Atmel Corporation

Specifications of AT32UC3L064

• Flash (kbytes): 64 Kbytes
• Pin Count: 48
• Max. Operating Frequency: 50 MHz
• Cpu: 32-bit AVR
• # Of Touch Channels: 17
• Hardware Qtouch Acquisition: Yes
• Max I/o Pins: 36
• Ext Interrupts: 36
• Usb Speed: No
• Usb Interface: No
• Spi: 5
• Twi (i2c): 2
• Uart: 4
• Lin: 4
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 12
• Adc Speed (ksps): 460
• Analog Comparators: 8
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 16
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.62 to 3.6
• Operating Voltage (vcc): 1.62 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 6
• Output Compare Channels: 18
• Input Capture Channels: 12
• Pwm Channels: 35
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

10.4.7
32099G–06/2011
SCIF
None.
Clock sources will not be stopped in Static mode if the difference between CPU and
PBx division factor is larger than 4
If the division factor between the CPU/HSB and PBx frequencies is more than 4 when enter-
ing a sleep mode where the system RC oscillator (RCSYS) is turned off, the high speed
clock sources will not be turned off. This will result in a significantly higher power consump-
tion during the sleep mode.
Fix/Workaround
Before going to sleep modes where RCSYS is stopped, make sure the division factor
between CPU/HSB and PBx frequencies is less than or equal to 4.
Disabling POR33 may generate spurious resets
Depending on operating conditions, POR33 may generate a spurious reset in one of the fol-
lowing cases:
In the listed cases, writing a one to the bit VREGCR.POR33MASK in the System Control
Interface (SCIF) to mask the POR33 reset will be ineffective
Fix/Workaround
- Do not disable POR33 using the user interface
- Do not use the SM33 supply monitor
- Do not enter Shutdown mode if a debugger is connected to the chip
Instability when exiting sleep walking
If all the following operating conditions are true, exiting sleep walking might lead to
instability:
- The OSC0 is enabled in external clock mode (OSCCTRL0.OSCEN == 1 and
OSCCTRL0.MODE == 0)
- A sleep mode where the OSC0 is automatically disabled is entered
- The device enters sleep walking
Fix/Workaround
Do not run OSC0 in external clock mode if sleepwalking is expected to be used.
Sleepwalking in idle and frozen sleep mode will mask all other PB clocks
If the CPU is in idle or frozen sleep mode and a module is in a state that triggers sleep walk-
ing, all PB clocks will be masked except the PB clock to the sleepwalking module.
Fix/Workaround
Mask all clock requests in the PM.PPCR register before going into idle or frozen mode.
VERSION register reads 0x400
The VERSION register reads 0x400 instead of 0x411.
Fix/Workaround
None.
The DFLL should be slowed down before disabling it
The frequency of the DFLL should be set to minimum before disabling it.
Fix/Workaround
Before disabling the DFLL the value of the COARSE register should be zero.
Writing to ICR masks new interrupts received in the same clock cycle
- When POR33 is disabled from the user interface
- When SM33 supply monitor is enabled
- When entering Shutdown mode while debugging the chip using JTAG or aWire interface
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