AT32UC3L064 Atmel Corporation, AT32UC3L064 Datasheet - Page 96

• Manufacturer Part Number: AT32UC3L064
• Manufacturer: Atmel Corporation

Specifications of AT32UC3L064

• Flash (kbytes): 64 Kbytes
• Pin Count: 48
• Max. Operating Frequency: 50 MHz
• Cpu: 32-bit AVR
• # Of Touch Channels: 17
• Hardware Qtouch Acquisition: Yes
• Max I/o Pins: 36
• Ext Interrupts: 36
• Usb Speed: No
• Usb Interface: No
• Spi: 5
• Twi (i2c): 2
• Uart: 4
• Lin: 4
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 12
• Adc Speed (ksps): 460
• Analog Comparators: 8
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 16
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.62 to 3.6
• Operating Voltage (vcc): 1.62 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 6
• Output Compare Channels: 18
• Input Capture Channels: 12
• Pwm Channels: 35
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

10.4.8
10.4.9
10.4.10
32099G–06/2011
AST
WDT
FREQM
OSC32VERSION register reads 0x100 instead of 0x101.
Fix/Workaround
None.
VREGVERSION register reads 0x100
VREGVERSION register reads 0x100 instead of 0x101.
Fix/Workaround
None.
RC120MVERSION register reads 0x100
RC120MVERSION register reads 0x100 instead of 0x101.
Fix/Workaround
None.
AST wake signal is released one AST clock cycle after the BUSY bit is cleared
After writing to the Status Clear Register (SCR) the wake signal is released one AST clock
cycle after the BUSY bit in the Status Register (SR.BUSY) is cleared. If entering sleep mode
directly after the BUSY bit is cleared the part will wake up immediately.
Fix/Workaround
Read the Wake Enable Register (WER) and write this value back to the same register. Wait
for BUSY to clear before entering sleep mode.
Clearing the WDT in window mode
In window mode, if the WDT is cleared 2
the counter will be cleared, but will not exit the window. If this occurs, the SR.WINDOW bit
will not be cleared after clearing the WDT.
Fix/Workaround
Check SR.WINDOW immediately after clearing the WDT. If set then clear the WDT once
more.
Clearing the Watchdog Timer (WDT) counter in second half of timeout period will
issue a Watchdog reset
If the WDT counter is cleared in the second half of the timeout period, the WDT will immedi-
ately issue a Watchdog reset.
Fix/Workaround
Use twice as long timeout period as needed and clear the WDT counter within the first half
of the timeout period. If the WDT counter is cleared after the first half of the timeout period,
you will get a Watchdog reset immediately. If the WDT counter is not cleared at all, the time
before the reset will be twice as long as needed.
VERSION register reads 0x400
The VERSION register reads 0x400 instead of 0x402.
Fix/Workaround
None.
Measured clock (CLK_MSR) sources 15-17 are shifted
CLKSEL = 14 selects the RC120M AW clock, CLKSEL = 15 selects the RC120M clock, and
CLKSEL = 16 selects the RC32K clock as source for the measured clock (CLK_MSR).
TBAN
CLK_WDT cycles after entering the window,
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