AT32UC3L064 Atmel Corporation, AT32UC3L064 Datasheet - Page 89

• Manufacturer Part Number: AT32UC3L064
• Manufacturer: Atmel Corporation

Specifications of AT32UC3L064

• Flash (kbytes): 64 Kbytes
• Pin Count: 48
• Max. Operating Frequency: 50 MHz
• Cpu: 32-bit AVR
• # Of Touch Channels: 17
• Hardware Qtouch Acquisition: Yes
• Max I/o Pins: 36
• Ext Interrupts: 36
• Usb Speed: No
• Usb Interface: No
• Spi: 5
• Twi (i2c): 2
• Uart: 4
• Lin: 4
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 12
• Adc Speed (ksps): 460
• Analog Comparators: 8
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 16
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.62 to 3.6
• Operating Voltage (vcc): 1.62 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 6
• Output Compare Channels: 18
• Input Capture Channels: 12
• Pwm Channels: 35
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

10.2.11
10.2.12
10.2.13
32099G–06/2011
CAT
aWire
CHIP
CAT asynchronous wake will be delayed by one AST event period
If the CAT detects a condition the should asynchronously wake the device in static mode,
the asynchronous wake will not occur until the next AST event. For example, if the AST is
generating events to the CAT every 50ms, and the CAT detects a touch at t=9200ms, the
asynchronous wake will occur at t=9250ms.
Fix/Workaround
None.
CAT QMatrix sense capacitors discharged prematurely
At the end of a QMatrix burst charging sequence that uses different burst count values for
different Y lines, the Y lines may be incorrectly grounded for up to n-1 periods of the periph-
eral bus clock, where n is the ratio of the PB clock frequency to the GCLK_CAT frequency.
This results in premature loss of charge from the sense capacitors and thus increased vari-
ability of the acquired count values.
Fix/Workaround
Enable the 1kOhm drive resistors on all implemented QMatrix Y lines (CSA 1, 3, 5, 7, 9, 11,
13, and/or 15) by writing ones to the corresponding odd bits of the CSARES register.
aWire CPU clock speed robustness
The aWire memory speed request command counter warps at clock speeds below approxi-
mately 5kHz.
Fix/Workaround
None.
The aWire debug interface is reset after leaving Shutdown mode
If the aWire debug mode is used as debug interface and the program enters Shutdown
mode, the aWire interface will be reset when the part receives a wakeup either from the
WAKE_N pin or the AST.
Fix/Workaround
None.
In 3.3V Single Supply Mode, the Analog Comparator inputs affects the device’s ability
to start
When using the 3.3V Single Supply Mode the state of the Analog Comparator input pins can
affect the device’s ability to release POR reset. This is due to an interaction between the
Analog Comparator input pins and the POR circuitry. The issue is not present in the 1.8V
Supply Mode or the 3.3V Supply Mode with 1.8V Regulated I/O Lines.
Fix/Workaround
ACREFN (pin PA16) must be connected to GND until the POR reset is released and the
Analog Comparator inputs should not be driven higher than 1.0 V until the POR reset is
released.
Increased Power Consumption in VDDIO in sleep modes
If OSC0 is enabled in crystal mode when entering a sleep mode where the OSC0 is dis-
abled, this will lead to an increased power consumption in VDDIO.
Fix/Workaround
AT32UC3L016/32/64
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