AT90PWM216 Atmel Corporation, AT90PWM216 Datasheet
AT90PWM216
Specifications of AT90PWM216
Related parts for AT90PWM216
AT90PWM216 Summary of contents
Page 1
... Special Microcontroller Features – Low Power Idle, Noise Reduction, and Power Down Modes – Power On Reset and Programmable Brown Out Detection – Flag Array in Bit-programmable I/O Space (4 bytes) 8-bit Atmel Microcontroller with 16K Bytes In-System Programmable Flash AT90PWM216 AT90PWM316 7710F–AVR–09/11 ...
Page 2
... AVR microcontrollers manufactured on the same process technology. Min and Max val- ues will be available after the device is characterized. 7710F–AVR–09/11 ADC ADC Analog Input Diff Compar Revision First revision of parts AT90PWM216/316 Application One fluorescent ballast HID ballast, fluorescent ballast, Motor control 2 ...
Page 3
... Pin Configurations Figure 3-1. Figure 3-2. 7710F–AVR–09/11 SOIC 24-pin Package SOIC 32-pin Package AT90PWM216/316 3 ...
Page 4
... GND 5 (T0/PSCOUT22) PC2 6 (T1/PSCOUT23) PC3 7 (MISO/PSCOUT20) PB0 8 Mnemonic Type GND Power Ground: 0V reference AGND Power Analog Ground: 0V reference for analog part AT90PWM216/316 24 PB4 (AMP PB3 (AMP PC6 (ADC 1 0/ACMP1 21 AREF AGND 20 AVCC 19 PC5 (ADC 9 /AMP1+) 18 PC4 (ADC 8 /AMP1-) 17 Name, Function & Alternate Function ...
Page 5
... ADC8 (Analog Input Channel 8) PC4 AMP1- (Analog Differential Amplifier 1 Input Channel ) ADC9 (Analog Input Channel 9) PC5 I/O AMP1+ (Analog Differential Amplifier 1 Input Channel ) ADC10 (Analog Input Channel 10) PC6 I/O ACMP1 (Analog Comparator 1 Positive Input ) PC7 I/O D2A : DAC output AT90PWM216/316 Name, Function & Alternate Function (2) 5 ...
Page 6
... Notes: 4. Overview The AT90PWM216/316 is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the AT90PWM216/316 achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed. ...
Page 7
... CISC microcontrollers. The AT90PWM216/316 provides the following features: 16K bytes of In-System Programmable Flash with Read-While-Write capabilities, 512 bytes EEPROM, 1024 bytes SRAM, 53 general purpose I/O lines, 32 general purpose working registers,three Power Stage Controllers, two flex- ...
Page 8
... Port C is not available on 24 pins package. Port C also serves the functions of special features of the AT90PWM316 as listed on 7710F–AVR–09/11 AT90PWM216 device is available in SOIC 24-pin Package and does not have the D2A (DAC Out- put) brought out to I/0 pins. 68. AT90PWM216/316 page 71 ...
Page 9
... As inputs, Port D pins that are externally pulled low will source current if the pull-up resistors are activated. The Port D pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port D also serves the functions of various special features of the AT90PWM216/316 as listed on page 4 ...
Page 10
... The program memory is In-System Reprogrammable Flash memory. 7710F–AVR–09/11 Block Diagram of the AVR Architecture Program Flash Counter Program Memory Instruction Register Instruction Decoder Control Lines AT90PWM216/316 Data Bus 8-bit Status and Control Interrupt Unit General Purpose SPI Registrers Unit Watchdog ...
Page 11
... SPI, and other I/O functions. The I/O Memory can be accessed directly the Data Space locations following those of the Register File, 0x20 - 0x5F. In addition, the AT90PWM216/316 has Extended I/O space from 0x60 - 0xFF in SRAM where only the ST/STS/STD and LD/LDS/LDD instructions can be used. ...
Page 12
... Bit 1 – Z: Zero Flag The Zero Flag Z indicates a zero result in an arithmetic or logic operation. See the “Instruction Set Description” for detailed information. 7710F–AVR–09/ R/W R/W R/W R ⊕ V AT90PWM216/316 R/W R/W R/W R SREG 12 ...
Page 13
... R13 R14 R15 R16 R17 … R26 R27 R28 R29 R30 R31 Figure 5-2, each register is also assigned a data memory address, mapping them AT90PWM216/316 Addr. 0x00 0x01 0x02 0x0D 0x0E 0x0F 0x10 0x11 0x1A X-register Low Byte 0x1B X-register High Byte 0x1C ...
Page 14
... SP6 SP5 SP4 SP3 R/W R/W R/W R/W R/W R/W R/W R/W R/W R directly generated from the selected clock source for the CPU AT90PWM216/316 R26 (0x1A R28 (0x1C R30 (0x1E SP10 SP9 SP8 SPH SP2 SP1 SP0 SPL R/W R/W R/W R/W ...
Page 15
... Register File single clock cycle an ALU Single Cycle ALU Operation T1 clk CPU Total Execution Time Register Operands Fetch ALU Operation Execute Result Write Back for details. AT90PWM216/316 “Memory Program- “Interrupts” on page 56. The list also “ ...
Page 16
... EEPROM write sbi EECR, EEWE out SREG, r16 ; restore SREG value (I-bit) C Code Example char cSREG; cSREG = SREG; /* store SREG value */ /* disable interrupts during timed sequence */ _CLI(); EECR |= (1<<EEMWE); /* start EEPROM write */ EECR |= (1<<EEWE); SREG = cSREG; /* restore SREG value (I-bit) */ AT90PWM216/316 16 ...
Page 17
... Global Interrupt Enable sleep; enter sleep, waiting for interrupt ; note: will enter sleep before any pending ; interrupt(s) C Code Example _SEI(); /* set Global Interrupt Enable */ _SLEEP(); /* enter sleep, waiting for interrupt */ /* note: will enter sleep before any pending interrupt(s) */ AT90PWM216/316 17 ...
Page 18
... Boot Program section and Application Program section. The Flash memory has an endurance of at least 10,000 write/erase cycles. The AT90PWM216/316 Program Counter (PC bits wide, thus addressing the 16K program memory locations. The operation of Boot Program section and associated Boot Lock bits for software protection are described in detail in gramming” ...
Page 19
... When using register indirect addressing modes with automatic pre-decrement and post-incre- ment, the address registers X, Y, and Z are decremented or incremented. The 32 general purpose working registers, 64 I/O Registers, 160 Extended I/O Registers, and the 512 bytes of internal data SRAM in the AT90PWM216/316 are all accessible through all these addressing modes. The Register File is described in page 13 ...
Page 20
... EEPROM Data Memory The AT90PWM216/316 contains 512 bytes of data EEPROM memory organized as a sep- arate data space, in which single bytes can be read and written. The EEPROM has an endurance of at least 100,000 write/erase cycles. The access between the EEPROM and the CPU is described in the following, specifying the EEPROM Address Registers, the EEPROM Data Register, and the EEPROM Control Register ...
Page 21
... Read/Write Initial Value • Bits 15..9 – Reserved Bits These bits are reserved bits in the AT90PWM216/316 and will always read as zero. • Bits 8..0 – EEAR8..0: EEPROM Address The EEPROM Address Registers – EEARH and EEARL specify the EEPROM address in the 512 bytes EEPROM space. The EEPROM data bytes are addressed linearly between 0 and 511 ...
Page 22
... EEPROM Mode Bits Programming EEPM0 Time Operation 0 3.4 ms Erase and Write in one operation (Atomic Operation) 1 1.8 ms Erase Only 0 1.8 ms Write Only 1 – Reserved for future use AT90PWM216/316 “Boot Loader for details about Boot 22 ...
Page 23
... The calibrated Oscillator is used to time the EEPROM accesses. gramming time for EEPROM access from the CPU. Table 6-2. Symbol EEPROM write (from CPU) 7710F–AVR–09/11 EEPROM Programming Time. Number of Calibrated RC Oscillator Cycles 26368 AT90PWM216/316 Table 6-2 lists the typical pro- Typ Programming Time 3 ...
Page 24
... EECR,EEMWE ; Start eeprom write by setting EEWE sbi EECR,EEWE ret /* Wait for completion of previous write */ while(EECR & (1<<EEWE Set up address and data registers */ EEAR = uiAddress; EEDR = ucData; /* Write logical one to EEMWE */ EECR |= (1<<EEMWE); /* Start eeprom write by setting EEWE */ EECR |= (1<<EEWE); AT90PWM216/316 24 ...
Page 25
... Wait for completion of previous write */ while(EECR & (1<<EEWE Set up address register */ EEAR = uiAddress; /* Start eeprom read by writing EERE */ EECR |= (1<<EERE); /* Return data from data register */ return EEDR; the EEPROM data can be corrupted because the supply voltage is CC, AT90PWM216/316 reset Protection circuit can CC 25 ...
Page 26
... I/O Memory The I/O space definition of the AT90PWM216/316 is shown in All AT90PWM216/316 I/Os and peripherals are placed in the I/O space. All I/O locations may be accessed by the LD/LDS/LDD and ST/STS/STD instructions, transferring data between the 32 general purpose working registers and the I/O space. I/O registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions. In these registers, the value of single bits can be checked by using the SBIS and SBIC instructions ...
Page 27
... General Purpose I/O Register 3– GPIOR3 Bit Read/Write Initial Value 7710F–AVR–09/ GPIOR37 GPIOR36 GPIOR35 GPIOR34 GPIOR33 GPIOR32 GPIOR31 GPIOR30 R/W R/W R/W R AT90PWM216/316 GPIOR3 R/W R/W R/W R ...
Page 28
... I/O clock is halted. 7710F–AVR–09/11 presents the principal clock systems in the AVR and their distribution. All of the clocks 39. The clock systems are detailed below. Clock Distribution AT90PWM216/316 PSC0/1/2 General I/O ADC Modules ...
Page 29
... The Watchdog Oscillator is used for timing this real-time part of the start-up time. The number of WDT Oscillator cycles used for each time-out is shown in 7710F–AVR–09/11 The clock from the selected source is input to the AVR clock generator, and routed to Device Clocking Options Select AT90PWM216/316 AT90PWM216/316 System CKSEL3..0 ...
Page 30
... Number of Watchdog Oscillator Cycles = 5.0V) Typ Time-out ( Table 7-3. For ceramic resonators, the capacitor values given by Crystal Oscillator Connections C2 C1 AT90PWM216/316 “Watchdog Oscillator = 3.0V) Number of Cycles CC 4 (4,096 64K (65,536) Figure 7-2. Either a quartz crystal or a XTAL2 XTAL1 ...
Page 31
... Frequency Range (MHz) (2) 0.4 - 0.9 0.9 - 3.0 3.0 - 8.0 8.0 -16.0 1. The frequency ranges are preliminary values. Actual values are TBD. 2. This option should not be used with crystals, only with ceramic resonators. AT90PWM216/316 Table 7-3. Recommended Range for Capacitors C1 and C2 for Use with Crystals (pF) – Table ...
Page 32
... These options are intended for use with ceramic resonators and will ensure frequency stability at start-up. They can also be used with crystals when not operating close to the maximum fre- quency of the device, and if frequency stability at start-up is not important for the application. 304. Section “Calibration Byte”, page AT90PWM216/316 Additional Delay from Reset (V = 5.0V) ...
Page 33
... If the RSTDISBL fuse is programmed, this start-up time will be increased to 14CK + 4 ensure programming mode can be entered. 2. The device is shipped with this option selected CAL7 CAL6 CAL5 R/W R/W R/W Device Specific Calibration Value AT90PWM216/316 (1)(2) CKSEL3..0 0010 Additional Delay from Reset (V = 5.0V) CC (1) 14CK 14CK + 4.1 ms 14CK + ...
Page 34
... Internal PLL for PSC The internal PLL in AT90PWM216/316 generates a clock frequency that is 64x multiplied from nominally 1 MHz input. The source of the 1 MHz PLL input clock is the output of the internal RC Oscillator which is divided down to 1 MHz. See the The PLL is locked on the RC Oscillator and adjusting the RC Oscillator via OSCCAL Register will adjust the fast peripheral clock at the same time ...
Page 35
... Read/Write Initial Value • Bit 7..3 – Res: Reserved Bits These bits are reserved bits in the AT90PWM216/316 and always read as zero. • Bit 2 – PLLF: PLL Factor The PLLF bit is used to select the division factor of the PLL. If PLLF is set, the PLL output is 64Mhz. ...
Page 36
... External Clock Frequency Frequency Range MHz Start-up Times for the External Clock Selection Start-up Time from Power- Additional Delay from down and Power-save Reset ( AT90PWM216/316 XTAL2 XTAL1 GND = 5.0V) Recommended Usage CC 14CK BOD enabled 14CK + 4.1 ms Fast rising power ...
Page 37
... System Clock Prescaler The AT90PWM216/316 system clock can be divided by setting the Clock Prescale Register – CLKPR. This feature can be used to decrease power consumption when the requirement for processing power is low. This can be used with all clock source options, and it will affect the clock frequency of the CPU and all synchronous peripherals ...
Page 38
... AT90PWM216/316 CLKPS0 Clock Division Factor 128 0 256 1 Reserved 0 Reserved 1 Reserved 0 Reserved 1 Reserved 0 Reserved 1 Reserved 38 ...
Page 39
... To avoid the MCU entering the sleep mode unless it is the programmer’s purpose recommended to write the Sleep Enable (SE) bit to one just before the execution of the SLEEP instruction and to clear it immediately after waking up. 7710F–AVR–09/11 Table 8-1 presents the different clock systems in the AT90PWM216/316, and their – ...
Page 40
... When the SM2..0 bits are 110 and an external crystal/resonator clock option is selected, the SLEEP instruction makes the MCU enter Standby mode. This mode is identical to Power-down 7710F–AVR–09/11 , while allowing the other clocks to run. FLASH “Clock Sources” on page AT90PWM216/316 , clk , and clk , while allowing the I/O CPU FLASH “ ...
Page 41
... Active Clock Domains and Wake-up Sources in the Different Sleep Modes. Active Clock Domains (1) 1. Only recommended with external crystal or resonator selected as clock source. 2. Only level interrupt PRPSC2 PRPSC1 PRPSC0 PRTIM1 R/W R/W R AT90PWM216/316 Oscillator s Wake-up Sources ( ( ( ...
Page 42
... Refer to “CROSS REFERENCE REMOVED” for details on ADC operation. 8.6.2 Analog Comparator When entering Idle mode, the Analog Comparator should be disabled if not used. When entering ADC Noise Reduction mode, the Analog Comparator should be disabled. In other sleep modes, 7710F–AVR–09/11 AT90PWM216/316 42 ...
Page 43
... Digital CC page 235 and page 254 for details. AT90PWM216/316 for details on how to configure the Analog “Brown-out Detection” on page 47 ) are stopped, the input buffers of the device will for details on which pins are enabled. If the for details “ ...
Page 44
... Reset Sources The AT90PWM216/316 has four sources of reset: • Power-on Reset. The MCU is reset when the supply voltage is below the Power-on Reset threshold (V • External Reset. The MCU is reset when a low level is present on the RESET pin for longer than the minimum pulse length. • ...
Page 45
... V Rise Rate to ensure internal CC Power-on RESET signal 1. Values are guidelines only. 2. The Power-on Reset will not work unless the supply voltage has been below V Table 9-1. The POR is activated whenever V AT90PWM216/316 DATA BUS MCU Status Register (MCUSR) Delay Counters Clock CK TIMEOUT Condition Min ...
Page 46
... RESET MCU Start-up, RESET Extended Externally V POT V CC RESET TIME-OUT INTERNAL RESET Table 9-1) will generate a reset, even if the clock is not running. – on its positive edge, the delay counter starts the MCU after RST – has expired. TOUT AT90PWM216/316 CC V RST t TOUT 46 ...
Page 47
... Figure 9-4. 9.5 Brown-out Detection AT90PWM216/316 has an On-chip Brown-out Detection (BOD) circuit for monitoring the V level during operation by comparing fixed trigger level. The trigger level for the BOD can be selected by the BODLEVEL Fuses. The trigger level has a hysteresis to ensure spike free Brown-out Detection. The hysteresis on the detection level should be interpreted as V ...
Page 48
... RESET for details on operation of the Watchdog Timer. Watchdog Reset During Operation – – – AT90PWM216/316 increases above the trigger level CC if the voltage stays below the trigger level for lon BOT+ V BOT- t TOUT – ...
Page 49
... Internal Voltage Reference AT90PWM216/316 features an internal bandgap reference. This reference is used for Brown- out Detection. The V from the internal bandgap reference. In order to use the internal Vref necessary to configure it thanks to the REFS1 and REFS0 bits in the ADMUX register and to set an analog feature which requires it ...
Page 50
... Watchdog Timer AT90PWM216/316 has an Enhanced Watchdog Timer (WDT). The main features are: • Clocked from separate On-chip Oscillator • 3 Operating modes – Interrupt – System Reset – Interrupt and System Reset • Selectable Time-out period from 16ms to 8s • Possible Hardware fuse Watchdog always on (WDTON) for fail-safe mode Figure 9-7 ...
Page 51
... The following code example shows one assembly and one C function for turning off the Watch- dog Timer. The example assumes that interrupts are controlled (e.g. by disabling interrupts globally) so that no interrupts will occur during the execution of these functions. TABLE 2. Assembly Code Example 7710F–AVR–09/11 (1) AT90PWM216/316 51 ...
Page 52
... Clear WDRF in MCUSR */ MCUSR &= ~(1<<WDRF); /* Write logical one to WDCE and WDE */ /* Keep old prescaler setting to prevent unintentional time-out */ WDTCSR |= (1<<WDCE) | (1<<WDE); /* Turn off WDT */ WDTCSR = 0x00; __enable_interrupt(); 1. The example code assumes that the part specific header file is included. AT90PWM216/316 52 ...
Page 53
... WDTCSR |= (1<<WDCE) | (1<<WDE); /* Set new prescaler(time-out) value = 64K cycles (~0 WDTCSR = (1<<WDE) | (1<<WDP2) | (1<<WDP0); __enable_interrupt(); 1. The example code assumes that the part specific header file is included WDIF WDIE WDP3 R/W R/W R AT90PWM216/316 WDCE WDE WDP2 WDP1 R/W R/W R/W R WDP0 ...
Page 54
... Interrupt Mode 1 0 System Reset Mode Interrupt and System Reset 1 1 Mode x x System Reset Mode 1. For the WDTON Fuse “1” means unprogrammed while “0” means programmed. 55. AT90PWM216/316 Action on Time-out None Interrupt Reset Interrupt, then go to System Reset Mode Reset 54 ...
Page 55
... AT90PWM216/316 Typical Time-out at Cycles (2048) cycles 4K (4096) cycles 8K (8192) cycles 0.125 s Reserved = 5. 0.25 s 0.5 s 1.0 s 2.0 s 4 ...
Page 56
... AT90PWM216/316. For a general explanation of the AVR interrupt handling, refer to Interrupt Handling” ...
Page 57
... When the IVSEL bit in MCUCR is set, Interrupt Vectors will be moved to the start of the Boot Flash Section. The address of each Interrupt Vector will then be the address in this table added to the start address of the Boot Flash Section. shows reset and Interrupt Vectors placement for the various combinations of Reset and Interrupt Vectors Placement in AT90PWM216/316 IVSEL Reset Address 1 ...
Page 58
... When the BOOTRST Fuse is unprogrammed, the Boot section size set to 2K bytes and the IVSEL bit in the MCUCR Register is set before any interrupts are enabled, the most typical and general program setup for the Reset and Interrupt Vector Addresses in AT90PWM216/316 is: Address Labels Code ...
Page 59
... When the BOOTRST Fuse is programmed, the Boot section size set to 2K bytes and the IVSEL bit in the MCUCR Register is set before any interrupts are enabled, the most typical and general program setup for the Reset and Interrupt Vector Addresses in AT90PWM216/316 is: Address Labels Code ...
Page 60
... MCUCR, r16 ; Move interrupts to Boot Flash section ldi r16, (1<<IVSEL) out MCUCR, r16 ret /* Enable change of Interrupt Vectors */ MCUCR = (1<<IVCE); /* Move interrupts to Boot Flash section */ MCUCR = (1<<IVSEL); AT90PWM216/316 “Boot Loader Support – Read-While- for details on Boot Lock bits. 60 ...
Page 61
... Note that enabling the alternate function of some of the port pins does not affect the use of the other pins in the port as general digital I/O. 7710F–AVR–09/11 “Electrical Characteristics(1)” on page 301 Pxn C pin AT90PWM216/316 and Ground as indicated in Figure CC for a complete list of parameters ...
Page 62
... SLEEP: SLEEP CONTROL clk : I/O CLOCK I/O 1. WRx, WPx, WDx, RRx, RPx, and RDx are common to all pins within the same port. clk SLEEP, and PUD are common to all ports. 79, the DDxn bits are accessed at the DDRx I/O address, the AT90PWM216/316 Figure 11 DDxn Q CLR ...
Page 63
... Input 1 1 Input 0 X Output 1 X Output Figure 11-2, the PINxn Register bit and the preceding latch con- pd,max AT90PWM216/316 Pull-up Comment Default configuration after Reset. No Tri-state (Hi-Z) Yes Pxn will source current if ext. pulled low. No Tri-state (Hi-Z) No Output Low (Sink) No Output High (Source) ...
Page 64
... The out instruction sets the “SYNC LATCH” signal at the positive edge of through the synchronizer is 1 system clock period. pd SYSTEM CLK r16 INSTRUCTIONS out PORTx, r16 SYNC LATCH PINxn r17 AT90PWM216/316 XXX in r17, PINx 0x00 t pd, max t pd, min , a single signal transition on the pin will be delayed 0xFF ...
Page 65
... Figure 11-2, the digital input signal can be clamped to ground at the input of the “Alternate Port Functions” on page AT90PWM216/316 /2. CC 66. 65 ...
Page 66
... SLEEP, and PUD are common to all ports. All other signals are unique for each pin. summarizes the function of the overriding signals. The pin and port indexes from are not shown in the succeeding tables. The overriding signals are generated internally AT90PWM216/316 Figure 11-2 can be overridden by ...
Page 67
... Unless the Digital Input is used as a clock source, the module with the alternate function will use its own synchronizer. This is the Analog Input/output to/from alternate functions. The Analog signal is connected directly to the pad, and can be used bi- Input/Output directionally. AT90PWM216/316 67 ...
Page 68
... ADC6 (Analog Input Channel 6) INT2 AMP0+ (Analog Differential Amplifier 0 Input Channel ) AMP0- (Analog Differential Amplifier 0 Input Channel ) ADC5 (Analog Input Channel5 ) INT1 MOSI (SPI Master Out Slave In) PSCOUT21 output MISO (SPI Master In Slave Out) PSCOUT20 output AT90PWM216/316 – – IVSEL IVCE R ...
Page 69
... DDB0. When the SPI is enabled as a slave, the data direction of this pin is controlled by DDB0. When the pin is forced input, the pull-up can still be controlled by the PORTB0 and PUD bits. PSCOUT20: Output 0 of PSC 2. 7710F–AVR–09/11 AT90PWM216/316 . . . 69 ...
Page 70
... ADC7 Overriding Signals for Alternate Functions in PB3..PB0 PB3/AMP0- PB2/ADC5/INT1 AMP0ND ADC5D + In1en 0 In1en INT1 AMP0- ADC5 AT90PWM216/316 PB5/ADC6/ INT2 PB4/AMP0 ADC6D + In2en AMP0ND In2en 0 INT2 ADC6 AMP0+ PB1/MOSI/ ...
Page 71
... AMP1+ (Analog Differential Amplifier 1 Input Channel ) ADC8 (Analog Input Channel 8) PC4 AMP1- (Analog Differential Amplifier 1 Input Channel ) T1 (Timer 1 clock input) PC3 PSCOUT23 output T0 (Timer 0 clock input) PC2 PSCOUT22 output PSCIN1 (PSC 1 Digital Input) PC1 OC1B (Timer 1 Output Compare B) PSCOUT10 output (see note 4) PC0 INT3 AT90PWM216/316 Table 11-6. 71 ...
Page 72
... Figure 11-5 on page 66. Overriding Signals for Alternate Functions in PC7..PC4 PC6/ADC10/ PC7/D2A ACMP1 DAEN DAEN ADC10D 0 0 – ADC10 Amp1 AT90PWM216/316 PC5/ADC9/ PC4/ADC8/ AMP1+ AMP1 – 0 – ADC9D ADC8D 0 0 ADC9 Amp1+ ADC8 Amp1- 72 ...
Page 73
... Overriding Signals for Alternate Functions in PC3..PC0 PC3/T1/ PC2/T0/ PSCOUT23 PSCOUT22 PSCen23 PSCen22 1 1 PSCen23 PSCen22 PSCout23 PSCout22 T1 T0 AT90PWM216/316 PC1/PSCIN1/ PC0/INT3/ OC1B PSCOUT10 PSCen10 0 1 OC1Ben PSCen10 OC1B PSCout10 In3en In3en PSCin1 INT3 ...
Page 74
... MOSI_A (Programming & alternate SPI Master Out Slave In) PSCIN2 (PSC 2 Digital Input) OC1A (Timer 1 Output Compare A) MISO_A (Programming & alternate Master In SPI Slave Out) PSCIN0 (PSC 0 Digital Input ) CLKO (System Clock Output) PSCOUT00 output XCK (UART Transfer Clock) SS_A (Alternate SPI Slave Select) AT90PWM216/316 Table 11-9. 74 ...
Page 75
... DDD2. When the SPI is enabled as a slave, the data direction of this pin is controlled by DDD2. When the pin is forced input, the pull-up can still be controlled by the PORTD2 bit. • PSCIN0/CLKO – Bit 1 PCSIN0, PSC 0 Digital Input. 7710F–AVR–09/11 AT90PWM216/316 75 ...
Page 76
... ACMP0D ADC3D + In0en 0 In0en – INT0 ADC3 ACOMP0 ACMPM AT90PWM216/316 PD5/ADC2/ PD4/ADC1/RXD/ ACMP2 ICP1A/SCK_A RXEN + SPE • 0 MSTR • SPIPS PD4 • 0 PUD RXEN + SPE • 0 MSTR • SPIPS 0 0 SPE • MSTR • 0 SPIPS 0 – ...
Page 77
... SS MOSI_Ain Alternate Function XTAL2: XTAL Output ADC0 (Analog Input Channel 0) XTAL1: XTAL Input OC0B (Timer 0 Output Compare B) RESET# (Reset Input) OCD (On Chip Debug I/O) AT90PWM216/316 PD1/PSCIN0/ PD0/PSCOUT00/X CLKO CK/SS_A SPE • 0 MSTR • SPIPS 0 PD0 • PUD PSCen00 + SPE • 0 MSTR • ...
Page 78
... PVOV DIEOE DIEOV DI AIO 7710F–AVR–09/11 relates the alternate functions of Port E to the overriding signals shown in 66. PE2/ADC0/ XTAL2 ADC0D 0 Osc Output ADC0 AT90PWM216/316 PE0/RESET/ PE1/OC0B OCD OC0Ben 0 OC0B Osc / Clock input ...
Page 79
... PINC5 PINC4 R/W R/W R/W R/W N/A N/A N/A N PORTD7 PORTD6 PORTD5 PORTD4 R/W R/W R/W R DDD7 DDD6 DDD5 DDD4 R/W R/W R/W R AT90PWM216/316 PORTB3 PORTB2 PORTB1 PORTB0 R/W R/W R/W R DDB3 DDB2 DDB1 DDB0 R/W R/W R/W R PINB3 PINB2 PINB1 PINB0 R/W ...
Page 80
... – – – – – – – – AT90PWM216/316 PIND3 PIND2 PIND1 PIND0 R/W R/W R/W R/W N/A N/A N/A N – PORTE2 PORTE1 PORTE0 R R/W R/W R – ...
Page 81
... The I/O clock is halted in all sleep modes except Idle “Electrical Characteristics(1)” on page 28. If the level is sampled twice by the Watchdog Oscillator clock but disappears before ISC31 ISC30 ISC21 R/W R/W R Table AT90PWM216/316 ISC20 ISC11 ISC10 ISC01 R/W R/W R/W R 12-1. Edges on INT3..INT0 are registered asynchro- “ ...
Page 82
... When changing the ISCn1/ISCn0 bits, the interrupt must be disabled by clearing its Interrupt Enable bit in the EIMSK Register. Otherwise an interrupt can occur when the bits are changed R/W R/W R R/W R/W R AT90PWM216/316 INT3 INT2 INT1 R/W R/W R/W R INTF3 INTF2 INTF1 R/W ...
Page 83
... Alternatively, one of four taps from the prescaler can be used as a CLK_I/O ). The Tn/T0 pin is sampled once every system clock cycle by the pin synchronization T0 /clk clk I/O Synchronization AT90PWM216/316 /8, f /64, f CLK_I/O CLK_I/O pulse for each positive (CSn2 negative Edge Detector /256, or CLK_I/O Figure 13-1 ) ...
Page 84
... Since the edge detector uses ExtClk clk_I/O clk I/O T0 Synchronization T1 Synchronization clk 1. The synchronization logic on the input pins ( TSM ICPSEL1 – R/W R AT90PWM216/316 (1) Clear T1 Tn/T0) is shown in Figure 13- – – – – ...
Page 85
... TSM bit is set. Note that Timer/Counter1 and Timer/Counter0 share the same prescaler and a reset of this prescaler will affect both timers. 7710F–AVR–09/11 Table ICPSEL1 Description Select ICP1A as trigger for timer 1 input capture Select ICP1B as trigger for timer 1 input capture AT90PWM216/316 . 85 ...
Page 86
... Control Logic direction TOP BOTTOM Timer/Counter TCNTn = = 0 = OCRnx Fixed TOP Values = OCRnx TCCRnA TCCRnB AT90PWM216/316 Figure 14-1. For the actual 8. CPU accessible I/O Registers, 98. must be written to zero to enable TOVn (Int.Req.) Clock Select clk Tn Edge Tn Detector ( From Prescaler ) OCnA (Int.Req.) Waveform OCnA Generation OCnB (Int ...
Page 87
... TCNT0 for accessing Timer/Counter0 counter value and so on. The definitions in 7710F–AVR–09/11 Table 14-1 are also used extensively throughout the document. AT90PWM216/316 87 ...
Page 88
... OCR0A Register. The assignment is depen- dent on the mode of operation. See “Using the Output Compare Unit” on page 114. “Timer/Counter0 and Timer/Counter1 Prescalers” on page DATA BUS count clear TCNTn direction bottom AT90PWM216/316 for details. The compare match 83. TOVn (Int.Req.) Clock Select Edge Detector clk Tn ...
Page 89
... Signalize that TCNT0 has reached minimum value (zero). ). clk can be generated from an external or internal clock source present or not. A CPU write overrides (has priority over) all counter clear or T0 92. shows a block diagram of the Output Compare unit. AT90PWM216/316 in the following. T0 (“Modes of Operation” on page 92). “Modes of 89 ...
Page 90
... OCR0x value, the compare match will be missed, resulting in incorrect waveform generation. Similarly, do not write the TCNT0 value equal to BOTTOM when the counter is downcounting. 7710F–AVR–09/11 DATA BUS OCRnx = (8-bit Comparator ) top bottom Waveform Generator FOCn WGMn1:0 AT90PWM216/316 TCNTn OCFnx (Int.Req.) OCnx COMnx1:0 90 ...
Page 91
... OC0x Register performed on the next compare match. For compare output actions in the 7710F–AVR–09/11 COMnx1 Waveform COMnx0 D Generator FOCn D PORT D clk I/O See “8-bit Timer/Counter Register Description” on page 98. AT90PWM216/316 Figure 14-4 shows a simplified Q 1 OCnx Pin OCnx DDR 91 ...
Page 92
... The timing diagram for the CTC mode is shown in increases until a compare match occurs between TCNT0 and OCR0A, and then counter (TCNT0) is cleared. 7710F–AVR–09/11 Table 14-2 on page 98. For fast PWM mode, refer to Table 14-4 on page 91.). “Timer/Counter Timing Diagrams” on page Figure AT90PWM216/316 Table 14-3 on 99. 96. 14-5. The counter value (TCNT0) 92 ...
Page 93
... In fast PWM mode, the counter is incremented until the counter value matches the TOP value. The counter is then cleared at the following timer clock cycle. The timing diagram for the fast 7710F–AVR–09/ clk_I/O = ------------------------------------------------- - f ⋅ ⋅ ( OCnx OCRnx AT90PWM216/316 OCnx Interrupt Flag Set (COMnx1 OC0 ) 93 = ...
Page 94
... The TCNT0 value is in the timing diagram shown as a his Table 14-6 on page 99). The actual OC0x value will only be visible on the f clk_I ----------------- - OCnxPWM N 256 = f OC0 AT90PWM216/316 OCRnx Interrupt Flag Set OCRnx Update and TOVn Interrupt Flag Set (COMnx1 (COMnx1 ⋅ /2 when OCR0A is set to zero. This clk_I/O 94 ...
Page 95
... OC0x pins. Setting the COM0x1:0 bits to two will produce a non-inverted PWM. An inverted PWM output can be generated by setting the COM0x1:0 to three: Setting the COM0A0 bits to 7710F–AVR–09/11 14-7. The TCNT0 value is in the timing diagram shown as a histogram for illustrating 1 AT90PWM216/316 OCnx Interrupt Flag Set OCRnx Update TOVn Interrupt Flag Set (COMnx1 ...
Page 96
... Figure 14-8 contains timing data for basic Timer/Counter operation. The figure I/O Tn /1) I/O MAX - 1 shows the same timing data, but with the prescaler enabled. AT90PWM216/316 100). The actual OC0x value will only be f clk_I/O = ----------------- - ⋅ N 510 OCnx has a transition from high to low even though Figure 14-7 ...
Page 97
... OCF0B in all modes and OCF0A in all modes except CTC I/O Tn /8) I/O OCRnx - 1 shows the setting of OCF0A and the clearing of TCNT0 in CTC mode and fast caler (f /8) clk_I/O I/O Tn /8) I/O TOP - 1 AT90PWM216/316 /8) clk_I/O MAX BOTTOM OCRnx OCRnx + 1 OCRnx Value TOP BOTTOM TOP BOTTOM + 1 /8) clk_I/O OCRnx + 2 ...
Page 98
... Clear OC0A on Compare Match, set OC0A at TOP 1 Set OC0A on Compare Match, clear OC0A at TOP 1. A special case occurs when OCR0A equals TOP and COM0A1 is set. In this case, the Com- pare Match is ignored, but the set or clear is done at TOP. See for more details. AT90PWM216/316 COM0B0 – ...
Page 99
... Set OC0B on Compare Match, clear OC0B at TOP 1. A special case occurs when OCR0B equals TOP and COM0B1 is set. In this case, the Com- pare Match is ignored, but the set or clear is done at TOP. See for more details. AT90PWM216/316 (1) “Phase Correct PWM Mode” on (1) “ ...
Page 100
... Note: • Bits 3, 2 – Res: Reserved Bits These bits are reserved bits in the AT90PWM216/316 and will always read as zero. • Bits 1:0 – WGM01:0: Waveform Generation Mode Combined with the WGM02 bit found in the TCCR0B Register, these bits control the counting ...
Page 101
... OCR0B as TOP. The FOC0B bit is always read as zero. • Bits 5:4 – Res: Reserved Bits These bits are reserved bits in the AT90PWM216/316 and will always read as zero. • Bit 3 – WGM02: Waveform Generation Mode See the description in the • Bits 2:0 – CS02:0: Clock Select The three Clock Select bits select the clock source to be used by the Timer/Counter ...
Page 102
... OC0B pin. 14.8.6 Timer/Counter Interrupt Mask Register – TIMSK0 Bit Read/Write Initial Value • Bits 7..3 – Res: Reserved Bits These bits are reserved bits in the AT90PWM216/316 and will always read as zero. 7710F–AVR–09/11 Clock Select Bit Description (Continued) CS01 CS00 Description 0 ...
Page 103
... Initial Value • Bits 7..3 – Res: Reserved Bits These bits are reserved bits in the AT90PWM216/316 and will always read as zero. • Bit 2 – OCF0B: Timer/Counter 0 Output Compare B Match Flag The OCF0B bit is set when a Compare Match occurs between the Timer/Counter and the data in OCR0B – ...
Page 104
... The PRTIM1 bit in Timer/Counter1 module. 7710F–AVR–09/11 “Pin Descriptions” on page “16-bit Timer/Counter Register Description” on page “Power Reduction Register” on page 41 AT90PWM216/316 Figure 15-1. For the actual 4. CPU accessible I/O Registers, 125. must be written to zero to enable 104 ...
Page 105
... Direction Timer/Counter TCNTn = OCRnA = OCRnB ICRn TCCRnA Table on page 4 1. Refer to for Timer/Counter1 pin placement and description. The compare match event will also set the Compare Match Flag (OCFnx) AT90PWM216/316 (1) TOVn (Int.Req.) Clock Select clk Tn Edge Detector TOP BOTTOM ( From Prescaler ) = ...
Page 106
... The counter reaches the TOP when it becomes equal to the highest value in the count sequence. The TOP value can be assigned to be one of the fixed values: 0x00FF, 0x01FF, or 0x03FF the value stored in the OCRnA or ICRn Register. The assignment is dependent of the mode of operation. AT90PWM216/316 106 ...
Page 107
... For I/O Registers located in extended I/O map, “IN”, “OUT”, “SBIS”, “SBIC”, “CBI”, and “SBI” instructions must be replaced with instructions that allow access to extended I/O. Typically “LDS” and “STS” combined with “SBRS”, “SBRC”, “SBR”, and “CBR”. AT90PWM216/316 107 ...
Page 108
... For I/O Registers located in extended I/O map, “IN”, “OUT”, “SBIS”, “SBIC”, “CBI”, and “SBI” instructions must be replaced with instructions that allow access to extended I/O. Typically “LDS” and “STS” combined with “SBRS”, “SBRC”, “SBR”, and “CBR”. AT90PWM216/316 108 ...
Page 109
... For I/O Registers located in extended I/O map, “IN”, “OUT”, “SBIS”, “SBIC”, “CBI”, and “SBI” instructions must be replaced with instructions that allow access to extended I/O. Typically “LDS” and “STS” combined with “SBRS”, “SBRC”, “SBR”, and “CBR”. “Timer/Counter0 and Timer/Counter1 Prescalers” on page AT90PWM216/316 83. 109 ...
Page 110
... The clk can be generated from an external or internal clock source present or not. A CPU write overrides (has priority over) all counter clear “16-bit Timer/Counter1 with PWM” on page AT90PWM216/316 TOVn (Int.Req.) Clock Select Edge Detector clk Tn Control Logic ( From Prescaler ) ...
Page 111
... ICRn Register for defining the counter’s TOP value. In these cases the Waveform Genera- 7710F–AVR–09/11 DATA BUS TEMP (8-bit) ICRnH (8-bit) ICRnL (8-bit) ICRn (16-bit Register) WRITE ICPSEL1 ICPnA ICPnB AT90PWM216/316 Figure 15-3. The elements of (8-bit) TCNTnH (8-bit) TCNTnL (8-bit) TCNTn (16-bit Counter) ICNC ICES Noise Edge ICFn (Int ...
Page 112
... I/O bit location). For measuring frequency only, the clearing of the ICFn Flag is not required (if an interrupt handler is used). 7710F–AVR–09/11 106. 83). The edge detector is also identical. However, when the noise canceler is AT90PWM216/316 “Accessing 16-bit Registers” (Figure 13- 112 ...
Page 113
... Output Compare unit. The small “n” in the register and DATA BUS TEMP (8-bit) OCRnxH Buf. (8-bit) OCRnxL Buf. (8-bit) OCRnx Buffer (16-bit Register) OCRnxH (8-bit) OCRnxL (8-bit) OCRnx (16-bit Register) TOP BOTTOM AT90PWM216/316 104.) (8-bit) TCNTnH (8-bit) TCNTnL (8-bit) TCNTn (16-bit Counter) = (16-bit Comparator ) OCFnx (Int.Req.) Waveform Generator WGMn3:0 ...
Page 114
... Secondly the COMnx1:0 bits control the OCnx pin output source. schematic of the logic affected by the COMnx1:0 bit setting. The I/O Registers, I/O bits, and I/O pins in the figure are shown in bold. Only the parts of the general I/O Port Control Registers 7710F–AVR–09/11 106. AT90PWM216/316 “Accessing 16-bit Registers” Figure 15-5 shows a simplified 114 ...
Page 115
... A change of the COMnx1:0 bits state will have effect at the first compare match after the bits are written. For non-PWM modes, the action can be forced to have immediate effect by using the FOCnx strobe bits. 7710F–AVR–09/11 Waveform Generator I/O See “16-bit Timer/Counter Register Description” on page 125. Table 15-2 on page AT90PWM216/316 OCnx PORT ...
Page 116
... The timing diagram for the CTC mode is shown in increases until a compare match occurs with either OCRnA or ICRn, and then counter (TCNTn) is cleared. 7710F–AVR–09/11 AT90PWM216/316 114.) “Timer/Counter Timing Diagrams” on page Figure 15-6. The counter value (TCNTn) 123 ...
Page 117
... OCRnA is set to zero (0x0000). The waveform frequency clk_I -------------------------------------------------- - ⋅ OCnA 2 N AT90PWM216/316 OCnA Interrupt Flag Set or ICFn Interrupt Flag Set (Interrupt on TOP) (COMnA1 clk_I/O ⋅ OCRnA 117 ...
Page 118
... The OCRnA Register however, is double buffered. This feature allows the OCRnA I/O location 7710F–AVR–09/11 ( log TOP R = ---------------------------------- - FPWM log AT90PWM216/316 ) Figure 15-7. The figure OCRnx/TOP Update and TOVn Interrupt Flag Set and OCnA Interrupt Flag Set or ICFn Interrupt Flag Set (Interrupt on TOP) (COMnx1 (COMnx1 ...
Page 119
... The PWM resolution for the phase correct PWM mode can be fixed to 8-, 9-, or 10-bit, or defined by either ICRn or OCRnA. The minimum resolution allowed is 2-bit (ICRn or OCRnA set to 7710F–AVR–09/11 Table on page f clk_I ---------------------------------- - ⋅ ( OCnxPWM TOP = f /2 when OCRnA is set to zero (0x0000). This feature clk_I/O AT90PWM216/316 126). The actual OCnx ) 119 ...
Page 120
... TOP actively while the Timer/Counter is running in the phase correct mode can result in an unsymmetrical output. The reason for this can be found in the time of update of the OCRnx Reg- ister. Since the OCRnx update occurs at TOP, the PWM period starts and ends at TOP. This 7710F–AVR–09/11 AT90PWM216/316 ( ) log ...
Page 121
... Figure The PWM resolution for the phase and frequency correct PWM mode can be defined by either ICRn or OCRnA. The minimum resolution allowed is 2-bit (ICRn or OCRnA set to 0x0003), and 7710F–AVR–09/11 f OCnxPCPWM 15-9). AT90PWM216/316 Table on page f clk_I/O = --------------------------- - ⋅ ⋅ TOP 126). The ...
Page 122
... R = ---------------------------------- - PFCPWM Figure 15-9. The figure shows phase and frequency correct shows the output generated is, in contrast to the phase correct mode, symmetri- AT90PWM216/316 ( ) + 1 TOP log OCnA Interrupt Flag Set or ICFn Interrupt Flag Set (Interrupt on TOP) OCRnx/TOP Updateand TOVn Interrupt Flag Set ...
Page 123
... OCnxPFCPWM Figure 15-10 clk I/O clk Tn (clk /1) I/O TCNTn OCRnx - 1 OCRnx OCFnx shows the same timing data, but with the prescaler enabled. AT90PWM216/316 f clk_I/O = --------------------------- - ⋅ ⋅ TOP ) is therefore shown shows a timing diagram for the setting of OCFnx. OCRnx OCRnx + 1 OCRnx + 2 OCRnx Value Table on ...
Page 124
... FPWM) TCNTn TOP - 1 TOVn (FPWM) and ICFn (if used as TOP) OCRnx Old OCRnx Value (Update at TOP) shows the same timing data, but with the prescaler enabled. AT90PWM216/316 OCRnx OCRnx + 1 OCRnx Value TOP BOTTOM TOP TOP - 1 New OCRnx Value /8) clk_I/O OCRnx + 2 ...
Page 125
... TOP COM1A1 COM1A0 COM1B1 R/W R/W R Table 15-2 Compare Output Mode, non-PWM COMnA0/COMnB0 AT90PWM216/316 /8) clk_I/O TOP BOTTOM TOP TOP - 1 New OCRnx Value COM1B0 – – WGM11 R R shows the COMnx1:0 bit functionality when the Description Normal port operation, OCnA/OCnB disconnected ...
Page 126
... A special case occurs when OCRnA/OCRnB equals TOP and COMnA1/COMnB1 is set. “Phase Correct PWM Mode” on page 119. Table 15-5. Modes of operation supported by the Timer/Counter AT90PWM216/316 (1) Description Normal port operation, OCnA/OCnB disconnected. WGMn3 15: Toggle OC1A on Compare Match, OC1B disconnected (normal port operation). ...
Page 127
... CTC 0 1 (Reserved Fast PWM 1 1 Fast PWM ICNC1 ICES1 – WGM13 R/W R AT90PWM216/316 Update of x TOP OCRn 0xFFFF Immediate 0x00FF TOP 0x01FF TOP 0x03FF TOP OCRnA Immediate 0x00FF TOP 0x01FF TOP 0x03FF TOP ICRn BOTTOM OCRnA BOTTOM ...
Page 128
... I External clock source on Tn pin. Clock on falling edge External clock source on Tn pin. Clock on rising edge FOC1A FOC1B – R/W R AT90PWM216/316 – – – – Figure 0 – TCCR1C R 0 ...
Page 129
... OCR1A[15:8] OCR1A[7:0] R/W R/W R/W R OCR1B[15:8] OCR1B[7:0] R/W R/W R/W R See “Accessing 16-bit Registers” on page 106 ICR1[15:8] ICR1[7:0] R/W R/W R/W R AT90PWM216/316 R/W R/W R/W R See “Accessing 16-bit R/W R/W R/W R R/W R/W R/W R ...
Page 130
... Initial Value • Bit 7, 6 – Res: Reserved Bits These bits are unused bits in the AT90PWM216/316, and will always read as zero. • Bit 5 – ICIE1: Timer/Counter1, Input Capture Interrupt Enable When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally enabled), the Timer/Counter1 Input Capture interrupt is enabled. The corresponding Interrupt Vector (see “ ...
Page 131
... Initial Value • Bit 7, 6 – Res: Reserved Bits These bits are unused bits in the AT90PWM216/316, and will always read as zero. • Bit 5 – ICF1: Timer/Counter1, Input Capture Flag This flag is set when a capture event occurs on the ICP1 pin. When the Input Capture Register (ICR1) is set by the WGMn3 used as the TOP value, the ICF1 Flag is set when the coun- ter reaches the TOP value ...
Page 132
... Zero crossing retriggering • Demagnetization retriggering • Fault input The PSC can be chained and synchronized to provide a configuration to drive three half bridges. Thanks to this feature it is possible to generate a three phase waveforms for applications such as Asynchronous or BLDC motor drive. 7710F–AVR–09/11 AT90PWM216/316 132 ...
Page 133
... PSC Counter = OCRnRB = OCRnSB Part B = OCRnRA = OCRnSA Part A PICRn PCNFn PFRCnB PCTLn PFRCnA AT90PWM216/316 Waveform PSCOUTn1 Generator B ( From Analog Comparator n Ouput ) PSC Input PSCn Input B Module B PISELnB PSCn Input A PSC Input Module A PSCINn PISELnA PSCOUTn0 Waveform Generator A ...
Page 134
... PSC Input = Module A OCRnRA Waveform = Generator A OCRnSA Part B PICRn PCNFn PFRCnB PCTLn PFRCnA (See “Output Matrix” on page AT90PWM216/316 PSCOUTn3 POS23 PSCOUTn1 ( From Analog Comparator n Ouput ) PSCn Input B Output PISELnB Matrix PSCn Input A PSCINn PISELnA PSCOUTn2 POS22 PSCOUTn0 POM2(PSC2 only) PSOCn 160 ...
Page 135
... PSC2 Internal Inputs Description Compare Value which Reset Signal on Part B (PSCOUTn1) Compare Value which Set Signal on Part B (PSCOUTn1) Compare Value which Reset Signal on Part A (PSCOUTn0) Compare Value which Set Signal on Part A (PSCOUTn0) AT90PWM216/316 PSCOUTn0 PSCOUTn1 (1) PSCOUTn2 (1) PSCOUTn3 PSCINn ...
Page 136
... Counter value at retriggering event PSC Interrupt Request : three souces, overflow, fault, and input capture ADC Synchronization (+ Amplifier Syncho. ) Stop Output (for synchronized mode) 1. See Figure 16-38 on page 161 2. See “Analog Synchronization” on page 160. AT90PWM216/316 Type Width Register 4 bits Signal Signal (1) Signal ...
Page 137
... Mode is like a one ramp mode which count down up and down. Notice that the update of a new set of values is done regardless of ramp Mode at the top of the last ramp. 7710F–AVR–09/11 PSC Cycle Sub-Cycle A Sub-Cycle B Ramp A0 Ramp A1 Ramp B0 Ramp B1 Ramp A Ramp B PSC Cycle AT90PWM216/316 UPDATE UPDATE 137 ...
Page 138
... One moment for PSCn0 description with OT0 which gives the time of the whole moment One moment for PSCn1 description with OT1 which gives the time of the whole moment 7710F–AVR–09/11 OCRnRA OCRnSA 0 On-Time 0 Dead-Time 0 PSC Cycle Minimal value for Dead-Time 0 and Dead-Time 1/Fclkpsc AT90PWM216/316 OCRnRB OCRnSB 0 On-Time 1 Dead-Time 1 138 ...
Page 139
... Dead-Time 1 = (OCRnSBH 1/Fclkpsc Note: 16.5.2.3 One Ramp Mode In One Ramp mode, PSCOUTn0 and PSCOUTn1 outputs can overlap each other. 7710F–AVR–09/11 OCRnRA OCRnSA 0 0 On-Time 0 Dead-Time 0 PSC Cycle Minimal value for Dead-Time 0 and Dead-Time 1 = 1/Fclkpsc AT90PWM216/316 OCRnRB OCRnSB On-Time 1 Dead-Time 1 139 ...
Page 140
... Dead-Time 0 = (OCRnSAH 1/Fclkpsc Dead-Time 1 = (OCRnSBH/L - OCRnRAH/L) * 1/Fclkpsc Note: 16.5.2.4 Center Aligned Mode In center aligned mode, the center of PSCn00 and PSCn01 signals are centered. 7710F–AVR–09/11 OCRnRA OCRnSA 0 On-Time 0 Dead-Time 0 PSC Cycle Minimal value for Dead-Time 0 = 1/Fclkpsc AT90PWM216/316 OCRnRB OCRnSB On-Time 1 Dead-Time 1 140 ...
Page 141
... PSC Counter OCRnRB OCRnSB OCRnSA On-Time 0 On-Time 1 PSCOUTn0 PSCOUTn1 Dead-Time PSC Cycle Minimal value for PSC Cycle = 2 * 1/Fclkpsc See “Analog Synchronization” on page 160. See “PSC 0 Control Register – PCTL0” on page AT90PWM216/316 0 On-Time 1 Dead-Time ). 0 167.(or PCTL1 or PCTL2) 141 ...
Page 142
... Cycles are grouped into frames of 16 cycles. Cycles are modulated by a sequence given by the 7710F–AVR–09/11 Regulation Loop Writting in Calculation PSC Registers Cycle Cycle Cycle Cycle With Set i With Set i With Set i With Set i page AT90PWM216/316 Request for an Update Cycle With Set j End of Cycle 165. 142 ...
Page 143
... Then the frequency resolution is divided by 16. In the example above, the resolution equals 25 Hz. 7710F–AVR–09/11 Δ – = period in a PSC cycle and is given by the following formula: PSC is the output operating frequency. f AVERAGE are two neightboring base frequencies AVERAGE AT90PWM216/316 × PLL PLL ------------------- - --------- - – ----------- - = PSC ...
Page 144
... prime cycle corresponding cycle AT90PWM216/316 is the nearest base frequency above the wanted The f and f frequencies are evenly distrib ...
Page 145
... PSCn PSCnCycle OT0 DT1 OT1 DT0 T1 144 ----- - = ---------------------------------------------------------------------- ( PSCn T OT0 ----- - = ------------------------------------------------------------------------------- - ( PSCn T OT0 2 d ----- - f = AVERAGE 16 AT90PWM216/316 Figure 16-6. f CLK_PSCn = = OT1 + DT0 + DT1 DT1 OT0 OT1 added on the PSCn0 signal while needed b2 SeeTable 16-5, “Distribution of fb2 in the modu- f CLK_PSCn ) + OT1 + DT0 + DT1 f CLK_PSCn ) 1 + ...
Page 146
... Digital 1 Filter 1 PFLTEnA CLK PSC (PFLTEnB) PISELnA (PISELnB) PELEVnA / PCAEnA 2 (PELEVnB) (PCAEnB) 4 PRFMnA3:0 (PRFMnB3:0) CLK PSC CLK PSC AT90PWM216/316 16.25.14page 170), PSCnIN0/1 input can act Input Processing (retriggering ...) PSC Core Output (Counter, Control PSCOUTn0 Waveform (PSCOUTn1) Generator, ...) (PSCOUT22) (PSCOUT23) 146 ...
Page 147
... On-Time 0 Dead-Time 0 Dead-Time 1 This example is given in “Input Mode 8” in “ ramp mode” See Figure 16-31. for details. On-Time 0 Dead-Time 0 This example is given in “Input Mode 1” in “ ramp mode” See Figure 16-20. for details. AT90PWM216/316 On-Time 1 On-Time 1 Dead-Time 1 147 ...
Page 148
... Dead-Time 0 This example is given in “Input Mode 1” in “ ramp mode” See Figure 16-20. for details. On level mode, it’s possible to use PSC to generate burst by using Input Mode 3 or Mode 4 ( See Figure 16-24. and Figure 16-25. for details.) AT90PWM216/316 On-Time 1 Dead-Time 0 On-Time 1 Dead-Time 1 Dead-Time 0 ...
Page 149
... Section “PSC n Input A Control Register – PFRCnA”, page 17016.25.14. 7710F–AVR–09/11 OFF is running. So thanks to PSC Asynchronous Output Control bit PSC CLK PSC Digital Filter 4 x CLK PSC PSC Input Module X AT90PWM216/316 BURST PSCn Input Ouput PSCOUTnX Stage PIN is running. PSC 149 ...
Page 150
... See “PSC Input Mode 9: Fixed Frequency Edge Retrigger PSC” on page 1001b 156. Reserved : Do not use 1010b 1011b 1100b 1101b See “PSC Input Mode 14: Fixed Frequency Edge Retrigger PSC and 1110b Disactivate Output” on page 157. Reserved : Do not use 1111b AT90PWM216/316 150 ...
Page 151
... When PSC Input B event occurs, PSC releases PSCOUTn1, waits for PSC Input B inactive state and then jumps and executes DT0 plus OT0. 7710F–AVR–09/11 DT0 OT0 OT1 DT0 OT0 DT1 OT1 OT1 AT90PWM216/316 DT1 DT0 OT0 DT1 OT1 DT0 OT0 DT1 OT1 OT1 ...
Page 152
... PSC Input B inactive state. Even if PSC Input B is released during DT0 or OT0, DT0 plus OT0 sub-cycle is always com- pletely executed. 7710F–AVR–09/11 DT0 OT0 DT1 OT1 OT1 DT0 OT0 DT1 OT1 OT1 AT90PWM216/316 DT0 OT0 DT1 DT0 OT0 DT1 OT1 OT1 152 ...
Page 153
... Even if PSC Input B is released during DT0 or OT0, DT0 plus OT0 sub-cycle is always com- pletely executed. 16.12 PSC Input Mode 4: Deactivate outputs without changing timing. 7710F–AVR–09/11 DT0 OT0 DT1 DT1 OT1 OT1 DT0 OT0 DT1 DT0 OT0 OT1 AT90PWM216/316 DT1 DT0 OT0 DT1 OT1 OT1 DT0 OT0 DT0 OT0 DT1 OT1 153 ...
Page 154
... Used in Fault mode 5, PSCn Input A or PSCn Input B act indifferently on On-Time0/Dead-Time0 or on On-Time1/Dead-Time1. 7710F–AVR–09/11 DT1 OT1 DT0 OT0 OT0 DT1 OT1 DT0 OT0 DT0 OT0 DT1 OT1 AT90PWM216/316 DT1 OT1 DT0 OT0 DT1 DT1 OT1 DT0 OT0 DT1 DT0 OT0 DT1 OT1 ...
Page 155
... Used in Fault mode 7, PSCn Input A or PSCn Input B act indifferently on On-Time0/Dead-Time0 or on On-Time1/Dead-Time1. 16.16 PSC Input Mode 8: Edge Retrigger PSC 7710F–AVR–09/11 DT0 OT0 DT1 OT1 DT0 OT0 DT1 OT1 1. Software action is the setting of the PRUNn bit in PCTLn register. AT90PWM216/316 DT0 OT0 DT1 OT1 DT1 DT0 OT0 DT1 Software Action (1) OT1 ...
Page 156
... Note: In one ramp mode, the retrigger event on input A resets the whole ramp. So the PSC doesn’t jump to the opposite dead-time. 16.17 PSC Input Mode 9: Fixed Frequency Edge Retrigger PSC 7710F–AVR–09/11 DT0 OT0 DT1 DT1 OT1 OT1 DT0 OT0 DT1 DT1 OT1 OT1 AT90PWM216/316 DT0 OT0 DT1 OT1 DT0 OT0 DT1 OT1 156 ...
Page 157
... The retrigger event is taken into account only if it occurs during the corresponding On-Time. 16.18 PSC Input Mode 14: Fixed Frequency Edge Retrigger PSC and Disactivate Output 7710F–AVR–09/11 DT0 OT0 DT1 DT1 OT1 DT0 OT0 DT1 OT1 AT90PWM216/316 DT0 OT0 OT1 DT1 DT0 OT0 DT1 OT1 DT1 OT1 OT1 ...
Page 158
... OT1 OT1 Available Input Modes according to Running Modes 1 Ramp Mode 2 Ramp Mode Valid Valid Do not use Valid Do not use Valid Valid Valid Do not use Valid AT90PWM216/316 DT0 OT0 DT0 OT0 DT1 OT1 DT0 OT0 DT0 OT0 DT1 OT1 4 Ramp Mode Valid ...
Page 159
... Available Input Modes according to Running Modes 1 Ramp Mode 2 Ramp Mode Do not use Valid Valid Valid Valid Valid Valid Valid Do not use Valid Valid Do not use AT90PWM216/316 4 Ramp Mode Centered Mode Valid Do not use Valid Valid Valid Do not use Valid Do not use Valid Do not use 159 ...
Page 160
... Analog Synchronization PSC generates a signal to synchronize the sample and hold; synchronisation is mandatory for measurements. 7710F–AVR–09/11 Output Matrix versus ramp number Ramp 0 Ramp 1 POMV2A0 POMV2A1 POMV2B0 POMV2B1 Output Matrix AT90PWM216/316 Ramp 2 Ramp 3 POMV2A2 POMV2A3 POMV2B2 POMV2B3 PSCOUT20 0 PSCOUT22 1 POS22 POS23 ...
Page 161
... PRUN0 PARUN0 PRUN1 PARUN1 PRUN2 PARUN2 If the PSCm has its PARUNn bit set, then it can start at the same time than PSCn-1. 7710F–AVR–09/11 SY0In Run PSC0 PSC0 SY0Out SY1In Run PSC1 PSC1 SY1Out SY2In Run PSC2 PSC2 SY2Out AT90PWM216/316 161 ...
Page 162
... PCLKSELn bit in PSC n Configuration register (PCNFn) is used to select the clock source. PPREn1/0 bits in PSC n Control Register (PCTLn) are used to select the divide factor of the clock. 7710F–AVR–09/11 1 PLL CK 0 I/O PCLKSELn AT90PWM216/316 See “PSC 0 Control Register – PCTL0” PRESCALER PPREn1/0 CLK PSCn 162 ...
Page 163
... PSCn EC (End of Cycle): When enabled and when a match with OCRnRB occurs • PSCn CAPT (Capture Event): When enabled and one of the two following events occurs : retrigger, capture of the PSC counter or Synchro Error. See PSCn Interrupt Mask Register 16.24.2 PSC Interrupt Vectors in AT90PWM216/316 Table 16-10. PSC Interrupt Vectors Vector No. - ...
Page 164
... Send signal on match with OCRnRA (during counting down of PSC). The 0 min value of OCRnRA must be 1. Send signal on match with OCRnRA (during counting up of PSC). The 1 min value of OCRnRA must synchronization signal 1 no synchronization signal AT90PWM216/316 POEN0B - POEN0A R/W ...
Page 165
... OCRnSB[7: OCRnRB[15:12] OCRnRB[7: AT90PWM216/316 OCRnSA[11:8] OCRnSAH OCRnRA[11:8] OCRnRAH OCRnRAL OCRnSB[11:8] ...
Page 166
... PLOCK0 PMODE01 R/W R/W R/W R PFIFTY1 PLOCK1 PMODE11 PALOCK1 R/W R/W R/W R PFIFTY2 PALOCK2 PLOCK2 PMODE21 R/W R/W R/W R AT90PWM216/316 PMODE00 POP0 PCLKSEL0 - R/W R/W R/W R PMODE10 POP1 PCLKSEL1 - R/W R/W R/W R PMODE20 POP2 PCLKSEL2 POME2 R/W ...
Page 167
... PAOC0B R/W R/W R/W R PPRE00 Description 0 No divider on PSC input clock 1 Divide the PSC input clock Divide the PSC input clock Divide the PSC clock by 256 AT90PWM216/316 “PSC2 Outputs” on page PAOC0A PARUN0 PCCYC0 PRUN0 R/W R/W R/W R PCTL0 ...
Page 168
... PPRE11 PPRE10 PBFM1 PAOC1B R/W R/W R/W R PPRE10 Description 0 No divider on PSC input clock 1 Divide the PSC input clock Divide the PSC input clock Divide the PSC clock by 256 AT90PWM216/316 PAOC1A PARUN1 PCCYC1 PRUN1 R/W R/W R/W R PCTL1 168 ...
Page 169
... PPRE21 PPRE20 PBFM2 PAOC2B R/W R/W R/W R PPRE20 Description 0 No divider on PSC input clock 1 Divide the PSC input clock Divide the PSC input clock Divide the PSC clock by 256 AT90PWM216/316 PAOC2A PARUN2 PCCYC2 PRUN2 R/W R/W R/W R PCTL2 169 ...
Page 170
... PCAEnA PISELnA PELEVnA PFLTEnA R/W R/W R/W R PCAEnB PISELnB PELEVnB PFLTEnB R/W R/W R/W R AT90PWM216/316 PRFMnA3 PRFMnA2 PRFMnA1 PRFMnA0 R/W R/W R/W R PRFMnB3 PRFMnB2 PRFMnB1 PRFMnB0 R/W R/W R/W R PFRCnA PFRCnB 170 ...
Page 171
... PSC Input Mode 9: Fixed Frequency Edge Retrigger PSC Reserved (do not use) PSC Input Mode 14: Fixed Frequency Edge Retrigger PSC and Disactivate Output Reserved (do not use PCST0 – – – PICR0[7: AT90PWM216/316 PICR0[11: PICR0H PICR0L 171 ...
Page 172
... PCST2 – – – PICR2[7: POMV2B3 POMV2B2 POMV2B1 POMV2B0 R/W R/W R/W R AT90PWM216/316 PICR1[11: PICR2[11: POMV2A3 POMV2A2 POMV2A1 POMV2A0 ...
Page 173
... PSEIE1 PEVE1B R R R/W R PSEIE2 PEVE2B R R R/W R POAC0B POAC0A PSEI0 PEV0B R R R/W R AT90PWM216/316 PEVE0A - - PEOPE0 R R PEVE1A - - PEOPE1 R R PEVE2A - - PEOPE2 R ...
Page 174
... POAC1B POAC1A PSEI1 PEV1B R R R/W R POAC2B POAC2A PSEI2 PEV2B R R R/W R AT90PWM216/316 PEV1A PRN11 PRN10 PEOP1 R R PEV2A PRN21 PRN20 PEOP2 R R PIFR1 ...
Page 175
... The last event which has generated an interrupt occured during ramp 1 1 The last event which has generated an interrupt occured during ramp 2 0 The last event which has generated an interrupt occured during ramp 3 1 The last event which has generated an interrupt occured during ramp 4 AT90PWM216/316 175 ...
Page 176
... Serial Peripheral Interface – SPI The Serial Peripheral Interface (SPI) allows high-speed synchronous data transfer between the AT90PWM216/316 and peripheral devices or between several AVR devices. The AT90PWM216/316 SPI includes the following features: 17.1 Features • Full-duplex, Three-wire Synchronous Data Transfer • Master or Slave Operation • ...
Page 177
... SPI Data Register before the next character has been completely shifted in. Oth- erwise, the first byte is lost. In SPI Slave mode, the control logic will sample the incoming signal of the SCK pin. To ensure correct sampling of the clock signal, the frequency of the SPI clock should never exceed f 7710F–AVR–09/11 AT90PWM216/316 SHIFT ENABLE /4. clkio ...
Page 178
... SPI Pin Overrides Direction, Master SPI User Defined Input User Defined User Defined 1. See “Alternate Functions of Port B” on page 68 direction of the user defined SPI pins. AT90PWM216/316 “Alternate Port Direction, Slave SPI Input User Defined Input Input for a detailed description of how to define the 178 ...
Page 179
... Set MOSI and SCK output, all others input */ DDR_SPI = (1<<DD_MOSI)|(1<<DD_SCK); /* Enable SPI, Master, set clock rate fck/16 */ SPCR = (1<<SPE)|(1<<MSTR)|(1<<SPR0); /* Start transmission */ SPDR = cData; /* Wait for transmission complete */ while(!(SPSR & (1<<SPIF))) ; 1. The example code assumes that the part specific header file is included. AT90PWM216/316 179 ...
Page 180
... Read received data and return in r16,SPDR ret (1) /* Set MISO output, all others input */ DDR_SPI = (1<<DD_MISO); /* Enable SPI */ SPCR = (1<<SPE); /* Wait for reception complete */ while(!(SPSR & (1<<SPIF))) ; /* Return data register */ return SPDR; 1. The example code assumes that the part specific header file is included. AT90PWM216/316 180 ...
Page 181
... Note that programming port are always located on alternate SPI port. 7710F–AVR–09/ SPIPS – – R MISO,MOSI, SCK and SS. pins, MISO_A, MOSI_A, SCK_A and SS_A. pins, MISO_A, MOSI_A, SCK_A and SS_A. MISO,MOSI, SCK and SS. AT90PWM216/316 PUD – – IVSEL R R ...
Page 182
... Figure 17-3 and Figure 17-4 CPOL Functionality CPOL Leading Edge 0 Rising 1 Falling Figure 17-3 CPHA Functionality CPHA Leading Edge 0 Sample 1 Setup AT90PWM216/316 CPOL CPHA SPR1 SPR0 R/W R/W R/W R for an example. The CPOL functionality is sum- Trailing Edge Falling Rising and Figure 17-4 for an example ...
Page 183
... SPI Data Register. • Bit 5..1 – Res: Reserved Bits These bits are reserved bits in the AT90PWM216/316 and will always read as zero. • Bit 0 – SPI2X: Double SPI Speed Bit When this bit is written logic one the SPI speed (SCK Frequency) will be doubled when the SPI is in Master mode (see clock periods ...
Page 184
... Sample (Falling) Setup (Falling) SCK (CPOL = 0) mode 0 SCK (CPOL = 1) mode 2 SAMPLE I MOSI/MISO CHANGE 0 MOSI PIN CHANGE 0 MISO PIN SS MSB first (DORD = 0) MSB Bit 6 LSB first (DORD = 1) LSB Bit 1 AT90PWM216/316 SPD3 SPD2 SPD1 R/W R/W R/W R Trailing eDge Setup (Falling) Sample (Falling) ...
Page 185
... SCK (CPOL = 0) mode 1 SCK (CPOL = 1) mode 3 SAMPLE I MOSI/MISO CHANGE 0 MOSI PIN CHANGE 0 MISO PIN SS MSB first (DORD = 0) MSB Bit 6 LSB first (DORD = 1) LSB Bit 1 AT90PWM216/316 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 LSB MSB 185 ...
Page 186
... Manchester framing error detection – Bit ordering configuration (MSB or LSB first) – Sleep mode exit under reception of EUSART frame 18.2 Overview A simplified block diagram of the USART Transmitter is shown in I/O Registers and I/O pins are shown in bold. 7710F–AVR–09/11 AT90PWM216/316 Figure 18-1. CPU accessible 186 ...
Page 187
... UBRR[H:L] BAUD RATE GENERATOR UDR (Transmit) TRANSMIT SHIFT REGISTER RECEIVE SHIFT REGISTER UDR (Receive) UCSRA 1. Refer to Pin Configurations3, Table 11-9 on page pin placement. AT90PWM216/316 Clock Generator CLKio SYNC LOGIC PIN CONTROL Transmitter TX CONTROL PARITY GENERATOR PIN CONTROL Receiver CLOCK ...
Page 188
... Transmitter clock (Internal Signal). Receiver base clock (Internal Signal). Input from XCK pin (internal Signal). Used for synchronous slave Clock output to XCK pin (Internal Signal). Used for synchronous master operation. clk System I/O Clock frequency. io AT90PWM216/316 clk Edge Detector UCPOLn Figure 18-2 ...
Page 189
... The baud rate is defined to be the transfer rate in bit per second (bps) Baud rate (in bits per second, bps). clk System I/O Clock frequency. io Contents of the UBRRH and UBRRL Registers, (0-4095). 210). Figure 18-2 for details. AT90PWM216/316 Equation for Calculating UBRR (1) Rate f CLKio ----------------------------------------- - UBRRn ( ...
Page 190
... It is therefore recommended io UCPOLn = 1 XCKn RxDn / TxDn UCPOLn = 0 XCKn RxDn / TxDn Figure 18-3 shows, when UCPOL is zero the data will be changed at illustrates the possible combinations of the frame formats. Bits inside brackets are AT90PWM216/316 Sample Sample 190 ...
Page 191
... even n 1 – ⊕ odd n 1 – Parity bit using even parity even odd Parity bit using odd parity Data bit n of the character n AT90PWM216/316 FRAME 3 4 [5] [6] [7] [8] [P] Sp1 [Sp2] … ⊕ ⊕ ⊕ ⊕ ⊕ ...
Page 192
... For I/O Registers located in extended I/O map, “IN”, “OUT”, “SBIS”, “SBIC”, “CBI”, and “SBI” instructions must be replaced with instructions that allow access to extended I/O. Typically “LDS” and “STS” combined with “SBRS”, “SBRC”, “SBR”, and “CBR”. AT90PWM216/316 192 ...
Page 193
... For I/O Registers located in extended I/O map, “IN”, “OUT”, “SBIS”, “SBIC”, “CBI”, and “SBI” instructions must be replaced with instructions that allow access to extended I/O. Typically “LDS” and “STS” combined with “SBRS”, “SBRC”, “SBR”, and “CBR”. AT90PWM216/316 . 193 ...
Page 194
... For I/O Registers located in extended I/O map, “IN”, “OUT”, “SBIS”, “SBIC”, “CBI”, and “SBI” instructions must be replaced with instructions that allow access to extended I/O. Typically “LDS” and “STS” combined with “SBRS”, “SBRC”, “SBR”, and “CBR”. AT90PWM216/316 194 ...
Page 195
... A second stop bit will be ignored by the Receiver. When the first stop bit is received, i.e., a complete serial frame is present in the Receive Shift Register, the contents of the Shift Register will be moved into the receive buffer. The receive buffer can then be read by reading the UDR I/O location. 7710F–AVR–09/11 AT90PWM216/316 195 ...
Page 196
... For I/O Registers located in extended I/O map, “IN”, “OUT”, “SBIS”, “SBIC”, “CBI”, and “SBI” instructions must be replaced with instructions that allow access to extended I/O. Typically “LDS” and “STS” combined with “SBRS”, “SBRC”, “SBR”, and “CBR”. AT90PWM216/316 196 ...
Page 197
... For I/O Registers located in extended I/O map, “IN”, “OUT”, “SBIS”, “SBIC”, “CBI”, and “SBI” instructions must be replaced with instructions that allow access to extended I/O. Typically “LDS” and “STS” combined with “SBRS”, “SBRC”, “SBR”, and “CBR”. AT90PWM216/316 197 ...
Page 198
... CH1 and CH2, CH3 is lost. When a Data OverRun condition is detected, the OverRun error is memorized. When the two characters CH1 and CH2 are read from the receive buffer, the DOR bit is set (and not before) and RxC remains set to warn the application about the overrun error. 7710F–AVR–09/11 AT90PWM216/316 198 ...
Page 199
... UDR I/O location until the RXC flag is cleared. The following code example shows how to flush the receive buffer. 7710F–AVR–09/11 CH1 CH2 CH3 and “Parity Checker” on page AT90PWM216/316 RxC=1 RxC=1 RxC=1 UDR=CH2 UDR=XX UDR=CH1 DOR=0 DOR=1 DOR=0 199 ...
Page 200
... I/O. Typically “LDS” and “STS” combined with “SBRS”, “SBRC”, “SBR”, and “CBR”. RxDn IDLE Sample (U2Xn = Sample (U2Xn = 1) AT90PWM216/316 START ...