AT90PWM216 Atmel Corporation, AT90PWM216 Datasheet - Page 190

• Manufacturer Part Number: AT90PWM216
• Manufacturer: Atmel Corporation

Specifications of AT90PWM216

• Flash (kbytes): 16 Kbytes
• Pin Count: 24
• Max. Operating Frequency: 16 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 12
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 19
• Ext Interrupts: 4
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Uart: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 125
• Analog Comparators: 2
• Resistive Touch Screen: No
• Dac Channels: 1
• Dac Resolution (bits): 10
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 1
• Eeprom (bytes): 512
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 105
• I/o Supply Class: 2.7 to 5.5
• Operating Voltage (vcc): 2.7 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 4
• Output Compare Channels: 12
• Input Capture Channels: 1
• Pwm Channels: 7
• 32khz Rtc: No
• Calibrated Rc Oscillator: Yes

18.3.4
18.4
18.4.1
7710F–AVR–09/11
Serial Frame
Synchronous Clock Operation
Frame Formats
Note that
to add some margin to avoid possible loss of data due to frequency variations.
When synchronous mode is used (UMSEL = 1), the XCK pin will be used as either clock input
(Slave) or clock output (Master). The dependency between the clock edges and data sampling
or data change is the same. The basic principle is that data input (on RxD) is sampled at the
opposite XCK clock edge of the edge the data output (TxDn) is changed.
Figure 18-3. Synchronous Mode XCK Timing.
The UCPOL bit UCRSnC selects which XCK clock edge is used for data sampling and which is
used for data change. As
rising XCK edge and sampled at falling XCK edge. If UCPOL is set, the data will be changed at
falling XCK edge and sampled at rising XCK edge.
A serial frame is defined to be one character of data bits with synchronization bits (start and stop
bits), and optionally a parity bit for error checking.
The USART accepts all 30 combinations of the following as valid frame formats:
A frame starts with the start bit followed by the least significant data bit. Then the next data bits,
up to a total of nine, are succeeding, ending with the most significant bit. If enabled, the parity bit
is inserted after the data bits, before the stop bits. When a complete frame is transmitted, it can
be directly followed by a new frame, or the communication line can be set to an idle (high) state.
Figure 18-4
optional.
• 1 start bit
• 5, 6, 7, 8, or 9 data bits
• no, even or odd parity bit
• 1 or 2 stop bits
f
clk
UCPOLn = 1
UCPOLn = 0
illustrates the possible combinations of the frame formats. Bits inside brackets are
io
depends on the stability of the system clock source. It is therefore recommended
RxDn / TxDn
RxDn / TxDn
XCKn
XCKn
Figure 18-3
shows, when UCPOL is zero the data will be changed at
AT90PWM216/316
Sample
Sample
190