AT90PWM216 Atmel Corporation, AT90PWM216 Datasheet - Page 84

• Manufacturer Part Number: AT90PWM216
• Manufacturer: Atmel Corporation

Specifications of AT90PWM216

• Flash (kbytes): 16 Kbytes
• Pin Count: 24
• Max. Operating Frequency: 16 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 12
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 19
• Ext Interrupts: 4
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Uart: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 125
• Analog Comparators: 2
• Resistive Touch Screen: No
• Dac Channels: 1
• Dac Resolution (bits): 10
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 1
• Eeprom (bytes): 512
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 105
• I/o Supply Class: 2.7 to 5.5
• Operating Voltage (vcc): 2.7 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 4
• Output Compare Channels: 12
• Input Capture Channels: 1
• Pwm Channels: 7
• 32khz Rtc: No
• Calibrated Rc Oscillator: Yes

13.0.4
7710F–AVR–09/11
General Timer/Counter Control Register – GTCCR
Each half period of the external clock applied must be longer than one system clock cycle to
ensure correct sampling. The external clock must be guaranteed to have less than half the sys-
tem clock frequency (f
sampling, the maximum frequency of an external clock it can detect is half the sampling fre-
quency (Nyquist sampling theorem). However, due to variation of the system clock frequency
and duty cycle caused by Oscillator source (crystal, resonator, and capacitors) tolerances, it is
recommended that maximum frequency of an external clock source is less than f
An external clock source can not be prescaled.
Figure 13-2. Prescaler for Timer/Counter0 and Timer/Counter1
Note:
• Bit 7 – TSM: Timer/Counter Synchronization Mode
Writing the TSM bit to one activates the Timer/Counter Synchronization mode. In this mode, the
value that is written to the PSRSYNC bit is kept, hence keeping the corresponding prescaler
reset signals asserted. This ensures that the corresponding Timer/Counters are halted and can
be configured to the same value without the risk of one of them advancing during configuration.
When the TSM bit is written to zero, the PSRSYNC bit is cleared by hardware, and the
Timer/Counters start counting simultaneously.
• Bit6 – ICPSEL1: Timer 1 Input Capture selection
Bit
Read/Write
Initial Value
PSRSYNC
1. The synchronization logic on the input pins (
clk
T0
T1
I/O
Synchronization
Synchronization
TSM
R/W
7
0
ExtClk
ICPSEL1
R/W
6
0
< f
clk_I/O
/2) given a 50/50% duty cycle. Since the edge detector uses
R
5
–
0
clk
Clear
T1
R
4
–
0
Tn/T0)
R
3
–
0
is shown in
R
2
–
0
AT90PWM216/316
(1)
Figure
R
1
–
0
13-1.
clk
PSRSYNC
T0
R/W
clk_I/O
0
0
/2.5.
GTCCR
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