ATmega168 Atmel Corporation, ATmega168 Datasheet - Page 284
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ATmega168
Manufacturer Part Number
ATmega168
Description
Manufacturer
Atmel Corporation
Specifications of ATmega168
Flash (kbytes)
16 Kbytes
Pin Count
32
Max. Operating Frequency
20 MHz
Cpu
8-bit AVR
# Of Touch Channels
16
Hardware Qtouch Acquisition
No
Max I/o Pins
23
Ext Interrupts
24
Usb Speed
No
Usb Interface
No
Spi
2
Twi (i2c)
1
Uart
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
15
Analog Comparators
1
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
1
Eeprom (bytes)
512
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8 to 5.5
Operating Voltage (vcc)
1.8 to 5.5
Fpu
No
Mpu / Mmu
no / no
Timers
3
Output Compare Channels
6
Input Capture Channels
1
Pwm Channels
6
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
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ATmega48/88/168
• Bit 5 – Res: Reserved bit
This bit is a reserved bit in the Atmel ATmega48/88/168 and always read as zero.
• Bit 4 – RWWSRE: Read-while-write section read enable
When programming (Page Erase or Page Write) to the RWW section, the RWW section is
blocked for reading (the RWWSB will be set by hardware). To re-enable the RWW section, the
user software must wait until the programming is completed (SELFPRGEN will be cleared).
Then, if the RWWSRE bit is written to one at the same time as SELFPRGEN, the next SPM
instruction within four clock cycles re-enables the RWW section. The RWW section cannot be
re-enabled while the Flash is busy with a Page Erase or a Page Write (SELFPRGEN is set). If
the RWWSRE bit is written while the Flash is being loaded, the Flash load operation will abort
and the data loaded will be lost.
• Bit 3 – BLBSET: Boot lock bit set
If this bit is written to one at the same time as SELFPRGEN, the next SPM instruction within four
clock cycles sets Boot Lock bits and Memory Lock bits, according to the data in R0. The data in
R1 and the address in the Z-pointer are ignored. The BLBSET bit will automatically be cleared
upon completion of the Lock bit set, or if no SPM instruction is executed within four clock cycles.
An LPM instruction within three cycles after BLBSET and SELFPRGEN are set in the SPMCSR
Register, will read either the Lock bits or the Fuse bits (depending on Z0 in the Z-pointer) into the
destination register. See
“Reading the fuse and lock bits from software” on page 277
for details.
• Bit 2 – PGWRT: Page write
If this bit is written to one at the same time as SELFPRGEN, the next SPM instruction within four
clock cycles executes Page Write, with the data stored in the temporary buffer. The page
address is taken from the high part of the Z-pointer. The data in R1 and R0 are ignored. The
PGWRT bit will auto-clear upon completion of a Page Write, or if no SPM instruction is executed
within four clock cycles. The CPU is halted during the entire Page Write operation if the NRWW
section is addressed.
• Bit 1 – PGERS: Page erase
If this bit is written to one at the same time as SELFPRGEN, the next SPM instruction within four
clock cycles executes Page Erase. The page address is taken from the high part of the Z-
pointer. The data in R1 and R0 are ignored. The PGERS bit will auto-clear upon completion of a
Page Erase, or if no SPM instruction is executed within four clock cycles. The CPU is halted dur-
ing the entire Page Write operation if the NRWW section is addressed.
• Bit 0 – SELFPRGEN: Self programming enable
This bit enables the SPM instruction for the next four clock cycles. If written to one together with
either RWWSRE, BLBSET, PGWRT or PGERS, the following SPM instruction will have a spe-
cial meaning, see description above. If only SELFPRGEN is written, the following SPM
instruction will store the value in R1:R0 in the temporary page buffer addressed by the Z-pointer.
The LSB of the Z-pointer is ignored. The SELFPRGEN bit will auto-clear upon completion of an
SPM instruction, or if no SPM instruction is executed within four clock cycles. During Page Erase
and Page Write, the SELFPRGEN bit remains high until the operation is completed.
Writing any other combination than “10001”, “01001”, “00101”, “00011” or “00001” in the lower
five bits will have no effect.
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2545T–AVR–05/11