ATmega32 Atmel Corporation, ATmega32 Datasheet - Page 112
![no-image](/images/manufacturer_photos/0/0/79/atmel_corporation_sml.jpg)
ATmega32
Manufacturer Part Number
ATmega32
Description
Manufacturer
Atmel Corporation
Specifications of ATmega32
Flash (kbytes)
32 Kbytes
Pin Count
44
Max. Operating Frequency
16 MHz
Cpu
8-bit AVR
# Of Touch Channels
16
Hardware Qtouch Acquisition
No
Max I/o Pins
32
Ext Interrupts
3
Usb Speed
No
Usb Interface
No
Spi
1
Twi (i2c)
1
Uart
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
15
Analog Comparators
1
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
2
Eeprom (bytes)
1024
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
2.7 to 5.5
Operating Voltage (vcc)
2.7 to 5.5
Fpu
No
Mpu / Mmu
no / no
Timers
3
Output Compare Channels
4
Input Capture Channels
1
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATmega32-16AC
Manufacturer:
COMPAL
Quantity:
500
Part Number:
ATmega32-16AU
Manufacturer:
ATMEL
Quantity:
20 000
Part Number:
ATmega32-16PI
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
Part Number:
ATmega32-16PU
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
Timer/Counter
Interrupt Mask
Register – TIMSK
Timer/Counter
Interrupt Flag Register
– TIFR
2503Q–AVR–02/11
(1)
The Input Capture is updated with the counter (TCNT1) value each time an event occurs on the
ICP1 pin (or optionally on the analog comparator output for Timer/Counter1). The Input Capture
can be used for defining the counter TOP value.
The Input Capture Register is 16-bit in size. To ensure that both the high and low bytes are read
simultaneously when the CPU accesses these registers, the access is performed using an 8-bit
temporary High Byte Register (TEMP). This temporary register is shared by all the other 16-bit
registers.
Note:
• Bit 5 – TICIE1: Timer/Counter1, Input Capture Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally
enabled), the Timer/Counter1 Input Capture Interrupt is enabled. The corresponding Interrupt
Vector
• Bit 4 – OCIE1A: Timer/Counter1, Output Compare A Match Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally
enabled), the Timer/Counter1 Output Compare A match interrupt is enabled. The corresponding
Interrupt Vector
TIFR, is set.
• Bit 3 – OCIE1B: Timer/Counter1, Output Compare B Match Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally
enabled), the Timer/Counter1 Output Compare B match interrupt is enabled. The corresponding
Interrupt Vector
TIFR, is set.
• Bit 2 – TOIE1: Timer/Counter1, Overflow Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally
enabled), the Timer/Counter1 Overflow Interrupt is enabled. The corresponding Interrupt Vector
(See “Interrupts” on page
Note:
Bit
Read/Write
Initial Value
Bit
Read/Write
Initial Value
(See “Interrupts” on page
1. This register contains interrupt control bits for several Timer/Counters, but only Timer1 bits are
This register contains flag bits for several Timer/Counters, but only Timer1 bits are described in
this section. The remaining bits are described in their respective timer sections.
See “Accessing 16-bit Registers” on page 89.
described in this section. The remaining bits are described in their respective timer sections.
OCIE2
OCF2
R/W
R/W
7
0
7
0
(See “Interrupts” on page
(See “Interrupts” on page
TOIE2
TOV2
R/W
R/W
6
0
6
0
44.) is executed when the TOV1 Flag, located in TIFR, is set.
TICIE1
ICF1
R/W
R/W
5
0
5
0
44.) is executed when the ICF1 Flag, located in TIFR, is set.
OCIE1A
OCF1A
R/W
R/W
4
0
4
0
44.) is executed when the OCF1A Flag, located in
44.) is executed when the OCF1B Flag, located in
OCIE1B
OCF1B
R/W
R/W
3
0
3
0
TOV1
TOIE1
R/W
R/W
2
0
2
0
OCIE0
OCF0
R/W
R/W
1
0
1
0
ATmega32(L)
TOV0
TOIE0
R/W
R/W
0
0
0
0
TIMSK
TIFR
112