ATmega32 Atmel Corporation, ATmega32 Datasheet - Page 71
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ATmega32
Manufacturer Part Number
ATmega32
Description
Manufacturer
Atmel Corporation
Specifications of ATmega32
Flash (kbytes)
32 Kbytes
Pin Count
44
Max. Operating Frequency
16 MHz
Cpu
8-bit AVR
# Of Touch Channels
16
Hardware Qtouch Acquisition
No
Max I/o Pins
32
Ext Interrupts
3
Usb Speed
No
Usb Interface
No
Spi
1
Twi (i2c)
1
Uart
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
15
Analog Comparators
1
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
2
Eeprom (bytes)
1024
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
2.7 to 5.5
Operating Voltage (vcc)
2.7 to 5.5
Fpu
No
Mpu / Mmu
no / no
Timers
3
Output Compare Channels
4
Input Capture Channels
1
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
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Manufacturer:
COMPAL
Quantity:
500
Part Number:
ATmega32-16AU
Manufacturer:
ATMEL
Quantity:
20 000
Part Number:
ATmega32-16PI
Manufacturer:
ATMEL/爱特梅尔
Quantity:
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Part Number:
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Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
Output Compare
Unit
2503Q–AVR–02/11
whether clk
count operations.
The counting sequence is determined by the setting of the WGM01 and WGM00 bits located in
the Timer/Counter Control Register (TCCR0). There are close connections between how the
counter behaves (counts) and how waveforms are generated on the Output Compare output
OC0. For more details about advanced counting sequences and waveform generation, see
“Modes of Operation” on page
The Timer/Counter Overflow (TOV0) Flag is set according to the mode of operation selected by
the WGM01:0 bits. TOV0 can be used for generating a CPU interrupt.
The 8-bit comparator continuously compares TCNT0 with the Output Compare Register
(OCR0). Whenever TCNT0 equals OCR0, the comparator signals a match. A match will set the
Output Compare Flag (OCF0) at the next timer clock cycle. If enabled (OCIE0 = 1 and Global
Interrupt Flag in SREG is set), the Output Compare Flag generates an output compare interrupt.
The OCF0 Flag is automatically cleared when the interrupt is executed. Alternatively, the OCF0
Flag can be cleared by software by writing a logical one to its I/O bit location. The waveform gen-
erator uses the match signal to generate an output according to operating mode set by the
WGM01:0 bits and Compare Output mode (COM01:0) bits. The max and bottom signals are
used by the waveform generator for handling the special cases of the extreme values in some
modes of operation
Figure 29
Figure 29. Output Compare Unit, Block Diagram
The OCR0 Register is double buffered when using any of the Pulse Width Modulation (PWM)
modes. For the normal and Clear Timer on Compare (CTC) modes of operation, the double buff-
ering is disabled. The double buffering synchronizes the update of the OCR0 Compare Register
to either top or bottom of the counting sequence. The synchronization prevents the occurrence
of odd-length, non-symmetrical PWM pulses, thereby making the output glitch-free.
shows a block diagram of the output compare unit.
T0
bottom
FOCn
top
is present or not. A CPU write overrides (has priority over) all counter clear or
(See “Modes of Operation” on page
OCRn
73.
Waveform Generator
WGMn1:0
=
(8-bit Comparator )
DATA BUS
COMn1:0
73.).
TCNTn
ATmega32(L)
OCFn (Int.Req.)
OCn
71