ATmega32A Atmel Corporation, ATmega32A Datasheet - Page 202

• Manufacturer Part Number: ATmega32A
• Manufacturer: Atmel Corporation

Specifications of ATmega32A

• Flash (kbytes): 32 Kbytes
• Pin Count: 44
• Max. Operating Frequency: 16 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 32
• Ext Interrupts: 3
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Twi (i2c): 1
• Uart: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 2
• Eeprom (bytes): 1024
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 2.7 to 5.5
• Operating Voltage (vcc): 2.7 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 3
• Output Compare Channels: 4
• Input Capture Channels: 1
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

20.9
20.9.1
8155C–AVR–02/11
Register Description
TWBR – TWI Bit Rate Register
Several different scenarios may arise during arbitration, as described below:
This is summarized in
Figure 20-21. Possible Status Codes Caused by Arbitration
• Bits 7:0 – TWI Bit Rate Register
TWBR selects the division factor for the bit rate generator. The bit rate generator is a frequency
divider which generates the SCL clock frequency in the Master modes. See
Unit” on page 182
Bit
Read/Write
Initial Value
• Two or more masters are performing identical communication with the same slave. In this
• Two or more masters are accessing the same slave with different data or direction bit. In this
• Two or more masters are accessing different slaves. In this case, arbitration will occur in the
case, neither the slave nor any of the masters will know about the bus contention.
case, arbitration will occur, either in the READ/WRITE bit or in the data bits. The masters
trying to output a one on SDA while another master outputs a zero will lose the arbitration.
Losing masters will switch to not addressed slave mode or wait until the bus is free and
transmit a new START condition, depending on application software action.
SLA bits. Masters trying to output a one on SDA while another master outputs a zero will lose
the arbitration. Masters losing arbitration in SLA will switch to slave mode to check if they are
being addressed by the winning master. If addressed, they will switch to SR or ST mode,
depending on the value of the READ/WRITE bit. If they are not being addressed, they will
switch to not addressed slave mode or wait until the bus is free and transmit a new START
condition, depending on application software action.
START
TWBR7
R/W
7
0
for calculating bit rates.
Address / General Call
Figure
Direction
received
TWBR6
Own
R/W
Yes
6
0
Arbitration lost in SLA
SLA
20-21. Possible status values are given in circles.
Write
Read
TWBR5
R/W
No
5
0
TWBR4
R/W
4
0
68/78
38
B0
Arbitration lost in Data
TWBR3
R/W
3
0
TWI bus will be released and not addressed slave mode will be entered
A START condition will be transmitted when the bus becomes free
Data byte will be received and NOT ACK will be returned
Data byte will be received and ACK will be returned
Last data byte will be transmitted and NOT ACK should be received
Data byte will be transmitted and ACK should be received
TWBR2
R/W
2
0
Data
TWBR1
R/W
1
0
ATmega32A
“Bit Rate Generator
TWBR0
R/W
0
0
STOP
TWBR
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