ATmega644P Atmel Corporation, ATmega644P Datasheet - Page 20

• Manufacturer Part Number: ATmega644P
• Manufacturer: Atmel Corporation

Specifications of ATmega644P

• Flash (kbytes): 64 Kbytes
• Pin Count: 44
• Max. Operating Frequency: 20 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 32
• Ext Interrupts: 32
• Usb Speed: No
• Usb Interface: No
• Spi: 3
• Twi (i2c): 1
• Uart: 2
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 4
• Eeprom (bytes): 2048
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8 to 5.5
• Operating Voltage (vcc): 1.8 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 3
• Output Compare Channels: 6
• Input Capture Channels: 1
• Pwm Channels: 6
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

5.3.1
8011O–AVR–07/10
Data Memory Access Times
The 32 general purpose working registers, 64 I/O registers, 160 Extended I/O Registers and the
1024/2048/4096 bytes of internal data SRAM in the ATmega164P/324P/644P are all accessible
through all these addressing modes. The Register File is described in
ter File” on page
Figure 5-2.
This section describes the general access timing concepts for internal memory access. The
internal data SRAM access is performed in two clk
Figure 5-3.
Address
clk
Data Memory Map for ATmega164P/324P/644P.
On-chip Data SRAM Access Cycles
Data
Data
WR
12.
CPU
RD
(1024/2048/4096 x 8)
160 Ext I/O Reg.
64 I/O Registers
Data Memory
Compute Address
Internal SRAM
32 Registers
T1
Memory Access Instruction
Address valid
ATmega164P/324P/644P
0x0000 - 0x001F
0x04FF/0x08FF/0x10FF
0x0020 - 0x005F
0x0060 - 0x00FF
0x0100
CPU
T2
cycles as described in
Next Instruction
T3
”General Purpose Regis-
Figure
5-3.
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