ATmega644P Atmel Corporation, ATmega644P Datasheet - Page 435

• Manufacturer Part Number: ATmega644P
• Manufacturer: Atmel Corporation

Specifications of ATmega644P

• Flash (kbytes): 64 Kbytes
• Pin Count: 44
• Max. Operating Frequency: 20 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 32
• Ext Interrupts: 32
• Usb Speed: No
• Usb Interface: No
• Spi: 3
• Twi (i2c): 1
• Uart: 2
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 4
• Eeprom (bytes): 2048
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8 to 5.5
• Operating Voltage (vcc): 1.8 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 3
• Output Compare Channels: 6
• Input Capture Channels: 1
• Pwm Channels: 6
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

8011O–AVR–07/10
18 2-wire Serial Interface .......................................................................... 207
19 AC - Analog Comparator ..................................................................... 237
20 ADC - Analog-to-digital Converter ..................................................... 240
21 JTAG Interface and On-chip Debug System ..................................... 260
18.1 Features .............................................................................................................207
18.2 2-wire Serial Interface Bus Definition .................................................................207
18.3 Data Transfer and Frame Format .......................................................................208
18.4 Multi-master Bus Systems, Arbitration and Synchronization ..............................211
18.5 Overview of the TWI Module ..............................................................................213
18.6 Using the TWI .....................................................................................................215
18.7 Transmission Modes ..........................................................................................218
18.8 Multi-master Systems and Arbitration .................................................................231
18.9 Register Description ...........................................................................................232
19.1 Overview ............................................................................................................237
19.2 Analog Comparator Multiplexed Input ................................................................237
19.3 Register Description ...........................................................................................238
20.1 Features .............................................................................................................240
20.2 Overview ............................................................................................................240
20.3 Operation ............................................................................................................241
20.4 Starting a Conversion .........................................................................................242
20.5 Prescaling and Conversion Timing .....................................................................243
20.6 Changing Channel or Reference Selection ........................................................246
20.7 ADC Noise Canceler ..........................................................................................248
20.8 ADC Conversion Result .....................................................................................253
20.9 Register Description ...........................................................................................255
21.1 Features .............................................................................................................260
21.2 Overview ............................................................................................................260
21.3 TAP – Test Access Port .....................................................................................260
21.4 TAP Controller ....................................................................................................262
21.5 Using the Boundary-scan Chain .........................................................................263
21.6 Using the On-chip Debug System ......................................................................263
21.7 On-chip Debug Specific JTAG Instructions ........................................................264
21.8 Using the JTAG Programming Capabilities ........................................................264
21.9 Bibliography ........................................................................................................265
21.10 Register Description .........................................................................................265
ATmega164P/324P/644P
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