ATmega644P Atmel Corporation, ATmega644P Datasheet - Page 84
ATmega644P
Manufacturer Part Number
ATmega644P
Description
Manufacturer
Atmel Corporation
Specifications of ATmega644P
Flash (kbytes)
64 Kbytes
Pin Count
44
Max. Operating Frequency
20 MHz
Cpu
8-bit AVR
# Of Touch Channels
16
Hardware Qtouch Acquisition
No
Max I/o Pins
32
Ext Interrupts
32
Usb Speed
No
Usb Interface
No
Spi
3
Twi (i2c)
1
Uart
2
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
15
Analog Comparators
1
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
4
Eeprom (bytes)
2048
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
Yes
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8 to 5.5
Operating Voltage (vcc)
1.8 to 5.5
Fpu
No
Mpu / Mmu
no / no
Timers
3
Output Compare Channels
6
Input Capture Channels
1
Pwm Channels
6
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
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8011O–AVR–07/10
• T0/XCK0/PCINT8, Bit 0
T0, Timer/Counter0 counter source.
XCK0, USART0 External clock. The Data Direction Register (DDB0) controls whether the clock
is output (DDD0 set “one”) or input (DDD0 cleared). The XCK0 pin is active only when the
USART0 operates in Synchronous mode.
PCINT8, Pin Change Interrupt source 8: The PB0 pin can serve as an external interrupt source.
Table 11-7
shown in
MISO signal, while MOSI is divided into SPI MSTR OUTPUT and SPI SLAVE INPUT. .
Table 11-7.
Table 11-8.
Signal
Name
PUOE
PUOV
DDOE
DDOV
PVOE
PVOV
DIEOE
DIEOV
DI
AIO
Signal
Name
PUOE
PUOV
DDOE
DDOV
PVOE
PVOV
DIEOE
DIEOV
DI
AIO
Figure 11-5 on page
PB7/SCK/
PCINT15
SPE • MSTR
PORTB7 • PUD
SPE • MSTR
0
SPE • MSTR
SCK OUTPUT
PCINT15 • PCIE1
1
SCK INPUT
PCINT17 INPUT
–
PB3/AIN1/OC0B/
PCINT11
0
0
0
0
OC0B ENABLE
OC0B
PCINT11 • PCIE1
1
PCINT11 INPUT
AIN1 INPUT
and
Overriding Signals for Alternate Functions in PB7:PB4
Overriding Signals for Alternate Functions in PB3:PB0
Table 11-8
relate the alternate functions of Port B to the overriding signals
78. SPI MSTR INPUT and SPI SLAVE OUTPUT constitute the
PB6/MISO/
PCINT14
SPE • MSTR
PORTB14 • PUD
SPE • MSTR
0
SPE • MSTR
SPI SLAVE
OUTPUT
PCINT14 • PCIE1
1
SPI MSTR INPUT
PCINT14 INPUT
–
PB2/AIN0/INT2/
PCINT10
0
0
0
0
0
0
INT2 ENABLE
PCINT10 • PCIE1
1
INT2 INPUT
PCINT10 INPUT
AIN0 INPUT
ATmega164P/324P/644P
PB5/MOSI/
PCINT13
SPE • MSTR
PORTB13 • PUD
SPE • MSTR
0
SPE • MSTR
SPI MSTR OUTPUT
PCINT13 • PCIE1
1
SPI SLAVE INPUT
PCINT13 INPUT
–
PB1/T1/CLKO/PCIN
T9
0
0
CKOUT
CKOUT
CKOUT
CLK I/O
PCINT9 • PCIE1
1
T1 INPUT
PCINT9 INPUT
–
PCINT12 • PCIE1
PB4/SS/OC0B/
PCINT12
SPE • MSTR
PORTB12 • PUD
SPE • MSTR
0
OC0A ENABLE
OC0A
1
SPI SS
PCINT12 INPUT
–
PB0/T0/XCK/
PCINT8
0
0
0
0
0
0
PCINT8 • PCIE1
1
T0 INPUT
PCINT8 INPUT
–
84