ATmega6450 Atmel Corporation, ATmega6450 Datasheet - Page 128
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ATmega6450
Manufacturer Part Number
ATmega6450
Description
Manufacturer
Atmel Corporation
Specifications of ATmega6450
Flash (kbytes)
64 Kbytes
Pin Count
100
Max. Operating Frequency
16 MHz
Cpu
8-bit AVR
Hardware Qtouch Acquisition
No
Max I/o Pins
69
Ext Interrupts
25
Usb Speed
No
Usb Interface
No
Spi
2
Twi (i2c)
1
Uart
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
15
Analog Comparators
1
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
4
Eeprom (bytes)
2048
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8 to 5.5
Operating Voltage (vcc)
1.8 to 5.5
Fpu
No
Mpu / Mmu
no / no
Timers
3
Output Compare Channels
4
Input Capture Channels
1
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
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17.11.8
17.11.9
2570N–AVR–05/11
TIMSK1 – Timer/Counter1 Interrupt Mask Register
TIFR1 – Timer/Counter1 Interrupt Flag Register
The Input Capture is updated with the counter (TCNT1) value each time an event occurs on the
ICP1 pin (or optionally on the Analog Comparator output for Timer/Counter1). The Input Capture
can be used for defining the counter TOP value.
The Input Capture Register is 16-bit in size. To ensure that both the high and low bytes are read
simultaneously when the CPU accesses these registers, the access is performed using an 8-bit
temporary High Byte Register (TEMP). This temporary register is shared by all the other 16-bit
registers.
• Bit 5 – ICIE1: Timer/Counter1, Input Capture Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally
enabled), the Timer/Counter1 Input Capture interrupt is enabled. The corresponding Interrupt
Vector
• Bit 2 – OCIE1B: Timer/Counter1, Output Compare B Match Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally
enabled), the Timer/Counter1 Output Compare B Match interrupt is enabled. The corresponding
Interrupt Vector
TIFR1, is set.
• Bit 1 – OCIE1A: Timer/Counter1, Output Compare A Match Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally
enabled), the Timer/Counter1 Output Compare A Match interrupt is enabled. The corresponding
Interrupt Vector
TIFR1, is set.
• Bit 0 – TOIE1: Timer/Counter1, Overflow Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally
enabled), the Timer/Counter1 Overflow interrupt is enabled. The corresponding Interrupt Vector
(See “Interrupts” on page
• Bit 5 – ICF1: Timer/Counter1, Input Capture Flag
This flag is set when a capture event occurs on the ICP1 pin. When the Input Capture Register
(ICR1) is set by the WGM13:0 to be used as the TOP value, the ICF1 Flag is set when the coun-
ter reaches the TOP value.
ICF1 is automatically cleared when the Input Capture Interrupt Vector is executed. Alternatively,
ICF1 can be cleared by writing a logic one to its bit location.
Bit
(0x6F)
Read/Write
Initial Value
Bit
0x16 (0x36)
Read/Write
Initial Value
(See “Interrupts” on page
See “Accessing 16-bit Registers” on page 104.
R
R
7
–
0
7
–
0
(See “Interrupts” on page
(See “Interrupts” on page
R
R
6
–
0
6
–
0
49.) is executed when the TOV1 Flag, located in TIFR1, is set.
ICIE1
ICF1
R/W
R/W
5
0
5
0
49.) is executed when the ICF1 Flag, located in TIFR1, is set.
R
4
–
R
0
4
–
0
49.) is executed when the OCF1B Flag, located in
49.) is executed when the OCF1A Flag, located in
ATmega325/3250/645/6450
R
R
3
–
0
3
–
0
OCIE1B
OCF1B
R/W
R/W
2
0
2
0
OCIE1A
OCF1A
R/W
R/W
1
0
1
0
TOIE1
TOV1
R/W
R/W
0
0
0
0
TIMSK1
TIFR1
128