ATmega6450 Atmel Corporation, ATmega6450 Datasheet - Page 45

• Manufacturer Part Number: ATmega6450
• Manufacturer: Atmel Corporation

Specifications of ATmega6450

• Flash (kbytes): 64 Kbytes
• Pin Count: 100
• Max. Operating Frequency: 16 MHz
• Cpu: 8-bit AVR
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 69
• Ext Interrupts: 25
• Usb Speed: No
• Usb Interface: No
• Spi: 2
• Twi (i2c): 1
• Uart: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 4
• Eeprom (bytes): 2048
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8 to 5.5
• Operating Voltage (vcc): 1.8 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 3
• Output Compare Channels: 4
• Input Capture Channels: 1
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

11.8
2570N–AVR–05/11
Watchdog Timer
Thus, when the BOD is not enabled, after setting the ACBG bit or enabling the ADC, the user
must always allow the reference to start up before the output from the Analog Comparator or
ADC is used. To reduce power consumption in Power-down mode, the user can avoid the three
conditions above to ensure that the reference is turned off before entering Power-down mode.
The Watchdog Timer is clocked from a separate On-chip Oscillator which runs at 1 MHz. This is
the typical value at V
controlling the Watchdog Timer prescaler, the Watchdog Reset interval can be adjusted as
shown in
dog Timer. The Watchdog Timer is also reset when it is disabled and when a Chip Reset occurs.
Eight different clock cycle periods can be selected to determine the reset period. If the reset
period expires without another Watchdog Reset, the Atmel ATmega325/3250/645/6450 resets
and executes from the Reset Vector. For timing details on the Watchdog Reset, refer to
11-2 on page
To prevent unintentional disabling of the Watchdog or unintentional change of time-out period,
two different safety levels are selected by the fuse WDTON as shown in Table 11-1. Refer to
“Timed Sequences for Changing the Configuration of the Watchdog Timer” on page 46
details.
Table 11-1.
Figure 11-7. Watchdog Timer
WDTON
Unprogrammed
Programmed
Table 11-2 on page
46.
WDT Configuration as a Function of the Fuse Settings of WDTON
Safety
Level
CC
1
2
= 5V. See characterization data for typical values at other V
OSCILLATOR
WATCHDOG
WDT Initial
State
Disabled
Enabled
46. The WDR – Watchdog Reset – instruction resets the Watch-
ATmega325/3250/645/6450
How to Disable the
WDT
Timed sequence
Always enabled
How to Change
Time-out
Timed sequence
Timed sequence
CC
levels. By
Table
for
45