ATmega6490 Atmel Corporation, ATmega6490 Datasheet - Page 229
ATmega6490
Manufacturer Part Number
ATmega6490
Description
Manufacturer
Atmel Corporation
Specifications of ATmega6490
Flash (kbytes)
64 Kbytes
Pin Count
100
Max. Operating Frequency
16 MHz
Cpu
8-bit AVR
# Of Touch Channels
16
Hardware Qtouch Acquisition
No
Max I/o Pins
69
Ext Interrupts
32
Usb Speed
No
Usb Interface
No
Spi
2
Twi (i2c)
1
Uart
1
Segment Lcd
160
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
15
Analog Comparators
1
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
4
Eeprom (bytes)
2048
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8 to 5.5
Operating Voltage (vcc)
1.8 to 5.5
Fpu
No
Mpu / Mmu
no / no
Timers
3
Output Compare Channels
4
Input Capture Channels
1
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
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23.1.3
23.1.4
23.1.5
2552K–AVR–04/11
LCD Clock Sources
LCD Prescaler
LCD Memory
Figure 23-1. LCD Module Block Diagram
The LCD Controller can be clocked by an internal synchronous or an external asynchronous
clock source. The clock source clk
LCDCS bit in the LCDCRB Register is written to logic one, the clock source is taken from the
TOSC1 pin.
The clock source must be stable to obtain accurate LCD timing and hence minimize DC voltage
offset across LCD segments.
The prescaler consist of a 12-bit ripple counter and a 1- to 8-clock divider. The LCDPS2:0 bits
selects clk
If a finer resolution rate is required, the LCDCD2:0 bits can be used to divide the clock further by
1 to 8.
Output from the clock divider clk
The display memory is available through I/O Registers grouped for each common terminal.
When a bit in the display memory is written to one, the corresponding segment is energized (on),
and non-energized when a bit in the display memory is written to zero.
D
A
T
A
B
U
S
LCD
divided by 16, 64, 128, 256, 512, 1024, 2048, or 4096.
LCDCRA
LCDCRB
LCDCCR
LCDFRR
LCDDR 19 -15
LCDDR 14 -10
TOSC
LCDDR 9 - 5
LCDDR 4 - 0
clk
i/o
lcdcc3:0
lcddc2:0
0
1
lcdcs
LATCH
array
LCD_PS
LCD Display Configuration
clk
LCD
Contrast Controller/
LCD
Power Supply
lcdps2:0
lcdcd2:0
is used as clock source for the LCD timing.
is by default equal to the system clock, clk
MUX
40 x
4:1
ATmega329/3290/649/6490
Divide by 1 to 8
12-bit Prescaler
LCD_voltage_ok
Multiplexer
LCD Ouput
Decoder
Timing
Clock
LCD
clk
LCD_PS
LCD Buffer/
Driver
CAP
LCD
1/3 V
1/2 V
2/3 V
V
LCD
LCD
LCD
LCD
Analog
Switch
Array
I/O
SEG35
SEG36
SEG37
SEG38
SEG39
COM0
COM1
COM2
COM3
SEG0
SEG1
SEG2
SEG3
SEG4
SEG5
. When the
229
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