ATUC64D3 Atmel Corporation, ATUC64D3 Datasheet - Page 282
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ATUC64D3
Manufacturer Part Number
ATUC64D3
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT32UC3A0128.pdf
(377 pages)
2.AT32UC3A0128.pdf
(33 pages)
3.AT32UC3A0128.pdf
(159 pages)
4.ATUC128D3.pdf
(755 pages)
5.ATUC128D3.pdf
(69 pages)
Specifications of ATUC64D3
Flash (kbytes)
64 Kbytes
Pin Count
64
Max. Operating Frequency
48 MHz
Cpu
32-bit AVR
# Of Touch Channels
25
Hardware Qtouch Acquisition
Yes
Max I/o Pins
51
Ext Interrupts
51
Usb Transceiver
1
Usb Speed
Full Speed
Usb Interface
Device
Spi
1
Twi (i2c)
2
Uart
3
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
16
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
3.0 to 3.6
Operating Voltage (vcc)
3.0 to 3.6
Fpu
No
Timers
3
Output Compare Channels
3
Input Capture Channels
3
Pwm Channels
7
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Available stocks
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Price
- AT32UC3A0128 PDF datasheet
- AT32UC3A0128 PDF datasheet #2
- AT32UC3A0128 PDF datasheet #3
- ATUC128D3 PDF datasheet #4
- ATUC128D3 PDF datasheet #5
- Current page: 282 of 377
- Download datasheet (5Mb)
282
AVR32
POPM – Pop Multiple Registers from Stack
Architecture revision:
Architecture revision1 and higher.
Description
Loads the consecutive words pointed to by SP into the registers specified in the instruction. The
PC can be loaded, resulting in a jump to the loaded value. If PC is popped, the return value in
R12 is tested and the flags are updated. R12 can optionally be updated with -1, 0 or 1. The k bit
in the instruction coding is used to optionally let the POPM instruction update the return register
R12 with the values -1, 0 or 1.
Operation:
I.
if Reglist8[PC] ∧ k == B’1
else
if Reglist8[5] == 1 then
if Reglist8[4] == 1 then
if Reglist8[3] == 1 then
if Reglist8[2] == 1 then
if Reglist8[1] == 1 then
PC ← *(SP++)
if Reglist8[LR:R12] == B’00
else if Reglist8[LR:R12] == B’01
else
Test R12 and update flags;
if Reglist8[PC] == 1 then
if Reglist8[LR] == 1 then
if Reglist8[R12] == 1 then
if Reglist8[PC] == 1 then
R11 ←*(SP++);
R10 ←*(SP++);
R9 ← *(SP++);
R8 ← *(SP++);
R7 ← *(SP++);
R6 ← *(SP++);
R5 ← *(SP++);
R4 ← *(SP++);
R3 ← *(SP++);
R12 ← 0;
R12 ← 1;
R12 ← −1;
PC ← *(SP++);
LR ← *(SP++);
R12 ←*(SP++);
Test R12 and update flags;
32000D–04/2011
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