ATUC64D3 Atmel Corporation, ATUC64D3 Datasheet - Page 33
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ATUC64D3
Manufacturer Part Number
ATUC64D3
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT32UC3A0128.pdf
(377 pages)
2.AT32UC3A0128.pdf
(33 pages)
3.AT32UC3A0128.pdf
(159 pages)
4.ATUC128D3.pdf
(755 pages)
5.ATUC128D3.pdf
(69 pages)
Specifications of ATUC64D3
Flash (kbytes)
64 Kbytes
Pin Count
64
Max. Operating Frequency
48 MHz
Cpu
32-bit AVR
# Of Touch Channels
25
Hardware Qtouch Acquisition
Yes
Max I/o Pins
51
Ext Interrupts
51
Usb Transceiver
1
Usb Speed
Full Speed
Usb Interface
Device
Spi
1
Twi (i2c)
2
Uart
3
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
16
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
3.0 to 3.6
Operating Voltage (vcc)
3.0 to 3.6
Fpu
No
Timers
3
Output Compare Channels
3
Input Capture Channels
3
Pwm Channels
7
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Available stocks
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- AT32UC3A0128 PDF datasheet
- AT32UC3A0128 PDF datasheet #2
- AT32UC3A0128 PDF datasheet #3
- ATUC128D3 PDF datasheet #4
- ATUC128D3 PDF datasheet #5
- Current page: 33 of 377
- Download datasheet (5Mb)
4.3
32000D–04/2011
Details on Secure State implementation
Figure 4-2.
Refer to the Technical Reference manual for the CPU core you are using for details on the
Secure State implementation.
Application
Bit 31
SP_APP
FINTPC
INT0PC
INT1PC
SMPC
R12
R11
R10
PC
LR
R9
R8
R7
R6
R5
R4
R3
R2
R1
R0
SR
Bit 0
Supervisor
Bit 31
RAR_SUP
RSR_SUP
SP_SYS
INT0PC
INT1PC
FINTPC
SMPC
Register File in AVR32B with secure context
R12
R11
R10
PC
SR
LR
R9
R8
R7
R6
R5
R4
R3
R2
R1
R0
Bit 0
INT0
Bit 31
LR / LR_INT0
(implementation
RAR_INT0
RSR_INT0
registers
SP_SYS
banked
defined)
PC
SR
Bit 0
INT1
Bit 31
LR / LR_INT1
(implementation
RSR_INT1
RAR_INT1
registers
SP_SYS
banked
defined)
PC
SR
Bit 0
INT2
Bit 31
LR / LR_INT2
(implementation
RSR_INT2
RAR_INT2
registers
SP_SYS
banked
defined)
PC
SR
SS_STATUS
SS_SP_APP
Bit 0
SS_SP_SYS
SS_ADRR
SS_ADRF
SS_ADR0
SS_ADR1
SS_RAR
SS_RSR
INT3
Bit 31
LR / LR_INT3
(implementation
RSR_INT3
RAR_INT3
registers
SP_SYS
banked
defined)
PC
SR
Bit 0
Exception
Bit 31
SP_SYS
RSR_EX
RAR_EX
INT0PC
INT1PC
FINTPC
SMPC
R12
R11
R10
PC
LR
SR
R9
R8
R7
R6
R5
R4
R3
R2
R1
R0
Bit 0
NMI
Bit 31
RSR_NMI
RAR_NMI
SP_SYS
INT0PC
INT1PC
FINTPC
SMPC
R12
R11
R10
PC
LR
R9
R8
R7
R6
R5
R4
R3
R2
R1
R0
SR
Bit 0
AVR32
Secure
Bit 31
SP_SEC
SS_RSR
SS_RAR
FINTPC
INT0PC
INT1PC
SMPC
R12
R11
R10
PC
LR
R9
R8
R7
R6
R5
R4
R3
R2
R1
R0
SR
Bit 0
33
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