ATUC64D3 Atmel Corporation, ATUC64D3 Datasheet - Page 6
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ATUC64D3
Manufacturer Part Number
ATUC64D3
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT32UC3A0128.pdf
(377 pages)
2.AT32UC3A0128.pdf
(33 pages)
3.AT32UC3A0128.pdf
(159 pages)
4.ATUC128D3.pdf
(755 pages)
5.ATUC128D3.pdf
(69 pages)
Specifications of ATUC64D3
Flash (kbytes)
64 Kbytes
Pin Count
64
Max. Operating Frequency
48 MHz
Cpu
32-bit AVR
# Of Touch Channels
25
Hardware Qtouch Acquisition
Yes
Max I/o Pins
51
Ext Interrupts
51
Usb Transceiver
1
Usb Speed
Full Speed
Usb Interface
Device
Spi
1
Twi (i2c)
2
Uart
3
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
16
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
3.0 to 3.6
Operating Voltage (vcc)
3.0 to 3.6
Fpu
No
Timers
3
Output Compare Channels
3
Input Capture Channels
3
Pwm Channels
7
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Available stocks
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Part Number
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Quantity
Price
- AT32UC3A0128 PDF datasheet
- AT32UC3A0128 PDF datasheet #2
- AT32UC3A0128 PDF datasheet #3
- ATUC128D3 PDF datasheet #4
- ATUC128D3 PDF datasheet #5
- Current page: 6 of 377
- Download datasheet (5Mb)
2.3
6
Instruction Organization
AVR32
AVR32 can access data of size byte, halfword, word and doubleword using dedicated instruc-
tions. The memory system can support unaligned accesses for selected load/store instructions
in some implementations. Any other unaligned access will cause an address exception.
For performance reasons, the user should make sure that the stack always is word aligned. This
means that only word instructions can be used to access the stack. When manipulating the
stack pointer, the user has to ensure that the result is word aligned before trying to load and
store data on the stack. Failing to do so will result in performance penalties. Code will execute
correctly if the stack is unaligned but with a significant performance penalty.
The AVR32 instruction set has both compact and extended instructions. Compact instructions
denotes the instructions which have a length of 16 bits while extended instructions have a length
of 32 bits.
All instructions must be placed on halfword boundaries, see
instructions can be both aligned and unaligned to halfword boundaries. In normal instruction
flow, the instruction buffer will always contain enough entries to ensure that compact, aligned
extended and unaligned extended instructions can be issued in a single cycle.
Change-of-flow operations such as branches, jumps, calls and returns may in some implemen-
tations require the instruction buffer to be flushed. The user should consult the Technical
Reference Manual for the specific implementation in order to determine how alignment of the
branch target address affects performance.
Table 2-2.
Byte Address
Byte Address
Instructions are stored in memory in a big endian fashion and must be aligned on
half word boundaries
0
0
H1
E2
C1
F2
D
A
I
1
1
2
2
H2
E1
C2
F1
G
B
J
3
3
Table 2-2 on page
Word Address
N+24
N+20
N+16
N+12
N+8
N+4
N
6. Extended
32000D–04/2011
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