ATUC64D3 Atmel Corporation, ATUC64D3 Datasheet - Page 67
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ATUC64D3
Manufacturer Part Number
ATUC64D3
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT32UC3A0128.pdf
(377 pages)
2.AT32UC3A0128.pdf
(33 pages)
3.AT32UC3A0128.pdf
(159 pages)
4.ATUC128D3.pdf
(755 pages)
5.ATUC128D3.pdf
(69 pages)
Specifications of ATUC64D3
Flash (kbytes)
64 Kbytes
Pin Count
64
Max. Operating Frequency
48 MHz
Cpu
32-bit AVR
# Of Touch Channels
25
Hardware Qtouch Acquisition
Yes
Max I/o Pins
51
Ext Interrupts
51
Usb Transceiver
1
Usb Speed
Full Speed
Usb Interface
Device
Spi
1
Twi (i2c)
2
Uart
3
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
16
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
3.0 to 3.6
Operating Voltage (vcc)
3.0 to 3.6
Fpu
No
Timers
3
Output Compare Channels
3
Input Capture Channels
3
Pwm Channels
7
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Available stocks
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- AT32UC3A0128 PDF datasheet
- AT32UC3A0128 PDF datasheet #2
- AT32UC3A0128 PDF datasheet #3
- ATUC128D3 PDF datasheet #4
- ATUC128D3 PDF datasheet #5
- Current page: 67 of 377
- Download datasheet (5Mb)
Table 8-1.
32000D–04/2011
Priority
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
Handler Address
0x8000_0000
for AVR32A.
0xA000_0000
for AVR32B.
Provided by OCD system
EVBA+0x00
EVBA+0x04
EVBA+0x08
EVBA+0x0C
EVBA+0x10
Autovectored
Autovectored
Autovectored
Autovectored
EVBA+0x14
EVBA+0x50
EVBA+0x18
EVBA+0x1C
EVBA+0x20
EVBA+0x24
EVBA+0x28
EVBA+0x2C
EVBA+0x30
EVBA+0x100
EVBA+0x34
EVBA+0x38
EVBA+0x60
EVBA+0x70
EVBA+0x3C
EVBA+0x40
EVBA+0x44
Priority and handler addresses for events
The interrupt system requires that an interrupt controller is present outside the core in order to
prioritize requests and generate a correct offset if more than one interrupt source exists for each
priority level. An interrupt controller generating different offsets depending on interrupt request
source is referred to as autovectoring. Note that the interrupt controller should generate
autovector addresses that do not conflict with addresses in use by other events or regular pro-
gram code.
Name
Reset
OCD Stop CPU
Unrecoverable exception
TLB multiple hit
Bus error data fetch
Bus error instruction fetch
NMI
Interrupt 3 request
Interrupt 2 request
Interrupt 1 request
Interrupt 0 request
Instruction Address
ITLB Miss
ITLB Protection
Breakpoint
Illegal Opcode
Unimplemented instruction
Privilege violation
Floating-point
Coprocessor absent
Supervisor call
Data Address (Read)
Data Address (Write)
DTLB Miss (Read)
DTLB Miss (Write)
DTLB Protection (Read)
DTLB Protection (Write)
DTLB Modified
Event source
External input
OCD system
Internal
Internal signal
Data bus
Data bus
External input
External input
External input
External input
External input
ITLB
ITLB
ITLB
OCD system
Instruction
Instruction
Instruction
FP Hardware
Instruction
Instruction
DTLB
DTLB
DTLB
DTLB
DTLB
DTLB
DTLB
Undefined
First non-completed instruction
First non-completed instruction
PC of offending instruction
PC of offending instruction
PC of offending instruction
PC(Supervisor Call) +2
Stored Return Address
First non-completed instruction
PC of offending instruction
PC of offending instruction
First non-completed instruction
First non-completed instruction
First non-completed instruction
First non-completed instruction
First non-completed instruction
PC of offending instruction
PC of offending instruction
First non-completed instruction
PC of offending instruction
PC of offending instruction
PC of offending instruction
PC of offending instruction
PC of offending instruction
PC of offending instruction
PC of offending instruction
PC of offending instruction
PC of offending instruction
PC of offending instruction
AVR32
67
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