ATUC64L4U Atmel Corporation, ATUC64L4U Datasheet - Page 111

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ATUC64L4U

Manufacturer Part Number
ATUC64L4U
Description
Manufacturer
Atmel Corporation
Datasheets

Specifications of ATUC64L4U

Flash (kbytes)
64 Kbytes
Pin Count
48
Max. Operating Frequency
50 MHz
Cpu
32-bit AVR
# Of Touch Channels
17
Hardware Qtouch Acquisition
Yes
Max I/o Pins
36
Ext Interrupts
36
Usb Transceiver
1
Usb Speed
Full Speed
Usb Interface
Device
Spi
1
Twi (i2c)
2
Uart
4
Lin
4
Ssc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
12
Adc Speed (ksps)
460
Analog Comparators
8
Resistive Touch Screen
No
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
16
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
Yes
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.62 to 3.6
Operating Voltage (vcc)
1.62 to 3.6
Fpu
No
Mpu / Mmu
Yes / No
Timers
6
Output Compare Channels
18
Input Capture Channels
12
Pwm Channels
35
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes

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9.3.3
32002F–03/2010
AUX port
Figure 9-4.
The Auxiliary (AUX) port and messaging protocol follow the definitions of the Nexus standard.
This standard allows varying the number of signalling pins. The following configuration is
selected for AVR32UC.
The configuration is based on the presumed needs for bandwidth in a system being traced at
100+ MIPS, balanced against the desire to keep debug pincount low. This configuration can be
changed in future implementations to allow for greater or smaller bandwidth over the AUX port.
The AUX pins may be multiplexed with GPIO in a device. By default, the MCKO, MDO, and
MSEO pins are tristated or used as GPIO, and the Nexus functionality must be explicitly enabled
by the debugger. EVTO, EVTI, and the JTAG pins are always available to the debugger.
If the AUX pins are needed for Nexus functionality in an application, it is recommended not to
use these pins for GPIO purposes, as this can affect the signal integrity required for Nexus
operation.
• 6 data output pins (MDO)
• 2 message start/end output pins (MSEO)
• 1 EVTO pin
• 1 EVTI pin
JTAG TAP controller state diagram.
1
0
Test-Logic-
Run-Test/
Reset
Idle
0
1
1
0
1
Capture-DR
Update-DR
Select-DR
Pause-DR
Exit1-DR
Exit2-DR
Shift-DR
Scan
0
0
1
0
1
1
0
0
0
1
1
1
0
1
Capture-IR
Update-IR
Select-IR
Pause-IR
Exit1-IR
Exit2-IR
Shift-IR
Scan
0
0
1
0
1
1
0
0
0
1
1
AVR32
111

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