ATUC64L4U Atmel Corporation, ATUC64L4U Datasheet - Page 37

• Manufacturer Part Number: ATUC64L4U
• Manufacturer: Atmel Corporation

Specifications of ATUC64L4U

• Flash (kbytes): 64 Kbytes
• Pin Count: 48
• Max. Operating Frequency: 50 MHz
• Cpu: 32-bit AVR
• # Of Touch Channels: 17
• Hardware Qtouch Acquisition: Yes
• Max I/o Pins: 36
• Ext Interrupts: 36
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 1
• Twi (i2c): 2
• Uart: 4
• Lin: 4
• Ssc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 12
• Adc Speed (ksps): 460
• Analog Comparators: 8
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 16
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.62 to 3.6
• Operating Voltage (vcc): 1.62 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 6
• Output Compare Channels: 18
• Input Capture Channels: 12
• Pwm Channels: 35
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

3.9.1.26
3.9.1.27
3.9.1.28
3.10
32002F–03/2010
Interrupt latencies
Floating-point Exception
Coprocessor Absent Exception
Supervisor call
Unused in AVR32UC.
The Coprocessor Absent exception is generated when a nonexisting coprocessor is addressed
by a coprocessor instruction. Used only if one or more coprocessors are present. Executing
coprocessor instructions in systems with no coprocessors results in an Unimplemented Instruc-
tion exception instead.
Supervisor calls are signalled by the application code executing a supervisor call (scall) instruc-
tion. The scall instruction behaves differently depending on which context it is called from. This
allows scall to be called from other contexts than Application.
When the exception routine is finished, execution continues at the instruction following scall. The
rets instruction is used to return from supervisor calls.
The following features in AVR32UC ensure low and deterministic interrupt latency:
• Four different interrupt levels and an NMI ensures that the user can efficiently prioritize the
• Long-running instructions such as ldm, stm, pushm, popm, divs and divu will be aborted if an
• Interrupts are autovectored, allowing the CPU to jump directly to the interrupt handler.
• When an interrupt of level m is received, the CPU will start stacking register file registers,
interrupt sources.
interrupt request is received. The slowest instruction that can not be aborted by a pending
interrupt has a worst case issue latency of 5 cycles. This implies that an interrupt request will
need to wait at most 5 cycles for an instruction to complete. The fastest instructions need
only a single cycle to complete.
return address and status register. After this stacking is performed, the CPU will jump to the
autovector address of the interrupt of level m. If an interrupt of level n, where n > m, is
received during this stacking, the CPU will jump to the autovector address of the interrupt of
level n, NOT the autovector address of the original interrupt.
*(--SP
*(--SP
SR[M2:M0] = B’110;
SR[EM] = 1;
SR[GM] = 1;
PC = EVBA | 0x30;
If ( SR[M2:M0] == {B’000 or B’001} )
else
*(--SP
*(--SP
PC ← EVBA | 0x100;
SR[M2:M0] ← B’001;
LR ← PC + 2;
PC ← EVBA | 0x100;
SYS
SYS
SYS
SYS
) = PC;
) = SR;
) = PC;
) = SR;
AVR32
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