ATUC64L4U Atmel Corporation, ATUC64L4U Datasheet - Page 40

• Manufacturer Part Number: ATUC64L4U
• Manufacturer: Atmel Corporation

Specifications of ATUC64L4U

• Flash (kbytes): 64 Kbytes
• Pin Count: 48
• Max. Operating Frequency: 50 MHz
• Cpu: 32-bit AVR
• # Of Touch Channels: 17
• Hardware Qtouch Acquisition: Yes
• Max I/o Pins: 36
• Ext Interrupts: 36
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 1
• Twi (i2c): 2
• Uart: 4
• Lin: 4
• Ssc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 12
• Adc Speed (ksps): 460
• Analog Comparators: 8
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 16
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.62 to 3.6
• Operating Voltage (vcc): 1.62 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 6
• Output Compare Channels: 18
• Input Capture Channels: 12
• Pwm Channels: 35
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

4. Floating Point Hardware
4.1
4.2
4.2.1
32002F–03/2010
Compliance
Operations
Floating point compare (fcp.s)
Newer versions of UC3 CPU introduced optional floating-point hardware performing 32-bit float-
ing-point operations. Instructions controlling this hardware are mapped into the coprocessor
instruction space, addressed as coprocessor 0. The CONFIG0 system register F bit indicates if
floating-point hardware is present on a specific AVR32 device.
The floating point hardware reads operands and places results in the same register file as the
traditional AVR32 instructions. Floating-point compare updates the flags in the AVR32 Status
Register, so that the regular AVR32 branch instructions can be used directly after a floating-
point compare.
The floating-point hardware consists of a fused multiply-accumulate unit, performing
as a single operation with no intermediate rounding, thereby resulting in greater precision than if
separate multiplication and addition had been performed. Hardware is also provided to convert
between integer and floating-point, to compare floating-point values, and to provide initial
approximations for reciprocal and reciprocal square root.
The floating point hardware conforms to the requirements of the C standard, which is based on
the IEEE 754 floating point standard.
The round-to-nearest, ties to even rounding mode is used for all instructions except float-to-inte-
ger conversions. Float-to-integer conversions use the round-to-zero mode.
The hardware supports denormal numbers.
Signalling NaN are not provided, all NaN are non-signalling (quiet). NaNs are not propagated,
the default quiet NaN is always returned (0x7FC00000).
No floating-point exceptions are generated.
The floating-point instructions are mapped into the coprocessor instruction space, but use the
ordinary integer register file. The ordinary integer instructions such as memory accesses and
logical operations can therefore be used on the same register data as the floating point hard-
ware uses. Therefore, no special floating-point data transfer instructions are required. All floating
point instructions are mapped to coprocessor 0 cop instructions, i.e. they are aliases for cop
instructions.
Attempting to execute instructions on any other coprocessor than coprocessor 0 will return a
coprocessor absent exception.
Attempting to execute coprocessor 0 instructions other than cop on a device with floating point
hardware will result in an unimplemented instruction exception.
Attempting to execute coprocessor 0 cop instructions on a device without floating point hard-
ware will result in an unimplemented instruction exception.
The floating point compare instruction, fcp.s, updates the status register flags. Ordinary AVR32
branch instructions such as breq and conditional instructions such as retge and movls can use
AVR32
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