ATUC64L4U Atmel Corporation, ATUC64L4U Datasheet - Page 6

• Manufacturer Part Number: ATUC64L4U
• Manufacturer: Atmel Corporation

Specifications of ATUC64L4U

• Flash (kbytes): 64 Kbytes
• Pin Count: 48
• Max. Operating Frequency: 50 MHz
• Cpu: 32-bit AVR
• # Of Touch Channels: 17
• Hardware Qtouch Acquisition: Yes
• Max I/o Pins: 36
• Ext Interrupts: 36
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 1
• Twi (i2c): 2
• Uart: 4
• Lin: 4
• Ssc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 12
• Adc Speed (ksps): 460
• Analog Comparators: 8
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 16
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.62 to 3.6
• Operating Voltage (vcc): 1.62 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 6
• Output Compare Channels: 18
• Input Capture Channels: 12
• Pwm Channels: 35
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

32002F–03/2010
Revision 3 of the AVR32UC CPU added the following system registers:
Revision 3 of the AVR32UC CPU added the following bit in the status register:
AVR32UC CPU revision 2 is fully backward-compatible with revision 1, ie. code compiled for
revision 1 is binary-compatible with revision 2 CPUs.
AVR32UC CPU revision 3 is fully backward-compatible with revision 1 and 2, ie. code compiled
for revision 1 and 2 is binary-compatible with revision 3 CPUs.
The Architecture Revision field in the CONFIG0 system register identifies which architecture
revision is implemented in a specific device. The “Processor and Architecture”-chapter of the
device datasheet identifies the CPU revision used.
• sscall
• retss
• Floating-point instructions as described in
• SS_STATUS
• SS_ADRF, SS_ADRR, SS_ADR0, SS_ADR1
• SS_SP_SYS, SS_SP_APP
• SS_RAR, SS_RSR
• SS
Section 4. on page
40.
AVR32
6